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ISP1761
Hi-Speed Universal Serial Bus On-The-Go controller
Rev. 01 -- 12 January 2005 Product data sheet
1. General description
The ISP1761 is a single-chip Hi-Speed Universal Serial Bus (USB) On-The-Go (OTG) Controller integrated with the advanced Philips Slave Host Controller and the Philips ISP1582 Peripheral Controller. The Hi-Speed USB Host Controller and Peripheral Controller comply to Universal Serial Bus Specification Rev. 2.0 and support data transfer speeds of up to 480 Mbit/s. The Enhanced Host Controller Interface (EHCI) core implemented in the Host Controller is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The OTG controller is compliant with On-The-Go Supplement to the USB Specification Rev. 1.0a. The ISP1761 has three USB ports. Port 1 can be configured to function as a downstream port, an upstream port or an OTG port; ports 2 and 3 are always configured as downstream ports. The OTG port can switch its role from host to peripheral, and peripheral to host. The OTG port can become a host through the Host Negotiation Protocol (HNP) as specified in the OTG supplement.
2. Features
s Compliant with Universal Serial Bus Specification Rev. 2.0; supporting data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) s Integrated Transaction Translator (TT) for Original USB (full-speed and low-speed) peripheral support s Three USB ports that support three operational modes: x Mode 1: Port 1 is an OTG Controller port, and ports 2 and 3 are Host Controller ports x Mode 2: Ports 1, 2 and 3 are Host Controller ports x Mode 3: Port 1 is a Peripheral Controller port, and ports 2 and 3 are Host Controller ports s Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) s Multitasking support with Virtual Segmentation feature (up to four banks) s High-speed memory controller (variable latency and SRAM external interface) s Directly addressable memory architecture s Generic processor interface to most CPUs, such as: Hitachi(R) SH-3 and SH-4, Philips XA, Intel(R) StrongARM(R), NEC(R) and Toshiba(R) MIPS, Motorola(R) DragonBallTM and PowerPC(R) Reduced Instruction Set Computer (RISC) processors s Configurable 32-bit and 16-bit external memory data bus s Supports Programmed I/O (PIO) and Direct Memory Access (DMA) s Slave DMA implementation on CPU interface for reducing the host system's CPU load
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
s Separate IRQ, DREQ and DACK lines for the Host Controller and the Peripheral Controller s Integrated multiconfiguration FIFO s Double-buffering scheme increases throughput and facilitates real-time data transfer s Integrated Phase-Locked Loop (PLL) with external 12 MHz crystal for low EMI s Tolerant I/O for low voltage CPU interface (1.65 V to 3.3 V) s 3.3 V-to-5.0 V external power supply input s Integrated 5.0 V-to-1.8 V or 3.3 V-to-1.8 V voltage regulator (internal 1.8 V for low-power core) s Internal power-on reset or low-voltage reset and block-dedicated software reset s Supports suspend and remote wake-up s Built-in overcurrent circuitry (analog overcurrent protection) s Hybrid-power mode: VCC(5V0) (can be switched off), VCC(I/O) (permanent) s Target total current consumption: x Normal operation; one port in high-speed active: ICC < 100 mA when the internal charge pump is not used x Suspend mode: ICC(susp) < 150 A at the room temperature s Available in LQFP128 and TFBGA128 packages s Host Controller-specific features x High performance USB host with integrated high-speed USB transceivers; supports high-speed, full-speed and low-speed x The EHCI core is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 x Configurable power management x Integrated TT for Original USB peripheral support on all three ports x Integrated 64 kB high-speed memory (internally organized as 8 k X 64 bits) x Additional 2.5 kB separate memory for TT x Individual or global overcurrent protection with built-in sense circuits x Overcurrent circuitry built-in (digital or analog overcurrent protection) s OTG Controller-specific features x OTG transceiver: fully integrated; compliant with On-The-Go Supplement to the USB Specification Rev. 1.0a x Supports HNP and SRP for OTG dual-role devices x HNP: status and control registers for software implementation x SRP: status and control registers for software implementation x Programmable timers with high resolution (0.01 ms to 80 ms)--for HNP and SRP x Supports external source of VBUS s Peripheral Controller-specific features x High-performance USB Peripheral Controller with integrated Serial Interface Engine (SIE), FIFO memory and transceiver x Complies with Universal Serial Bus Specification Rev. 2.0 and most device class specifications x Supports auto Hi-Speed USB mode discovery and Original USB fallback capabilities x Supports high-speed and full-speed on the Peripheral Controller x Bus-powered or self-powered capability with suspend mode
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Product data sheet
Rev. 01 -- 12 January 2005
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Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
x Slave DMA, fully autonomous and supports multiple configurations x Seven IN endpoints, seven OUT endpoints and one fixed control IN and OUT endpoint x Integrated 8 kB memory x Software-controllable connection to the USB bus, SoftConnectTM
3. Applications
The ISP1761 can be used to implement a dual-role USB device in any application--USB host or USB peripheral--depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role device can also be connected to a PC or any other USB host and behave like a typical USB peripheral.
3.1 Host/peripheral roles
s Mobile phone to/from: x Mobile phone: exchange contact information x Digital still camera: e-mail pictures or upload pictures to the web x MP3 player: upload/download/broadcast music x Mass storage: upload/download files x Scanner: scan business cards s Digital still camera to/from: x Digital still camera: exchange pictures x Mobile phone: e-mail pictures, upload pictures to the web x Printer: print pictures x Mass storage: store pictures s Printer to/from: x Digital still camera: print pictures x Scanner: print scanned image x Mass storage: print files stored in a device s MP3 player to/from: x MP3 player: exchange songs x Mass storage: upload/download songs s Oscilloscope to/from: x Printer: print screen image s Personal digital assistant to/from: x Personal digital assistant: exchange files x Printer: print files x Mobile phone: upload/download files x MP3 player: upload/download songs x Scanner: scan pictures x Mass storage: upload/download files x Global Positioning System (GPS): obtain directions, mapping information x Digital still camera: upload pictures x Oscilloscope: configure oscilloscope
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Product data sheet
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3 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
4. Ordering information
Table 1: Ordering information Name ISP1761BE ISP1761ET [1]
[1]
Type number Package Description plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm plastic thin fine-pitch ball grid array package; 128 balls; body 9 x 9 x 0.8 mm Version SOT425-1 SOT857-1 LQFP128 TFBGA128
The ISP1761ET is currently under development.
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Product data sheet
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ISP1761
Hi-Speed USB OTG controller
5. Block diagram
VCC(I/O)
37 to 39, 41 to 43, 45 to 47, 49, 51, 52, 54, 56 to 58, 60 to 62, 64 to 66, 68 to 70, 72 to 74, 76 to 78, 80 D[15:0]/D[31:0] 82, 84, 86, 87, 89, 91 to 93, 95 to 98, 100 to 103, 105 A[17:1] 106 107 108 111 112 113 114 116 117
10, 40, 48, 59, 67, 75, 83, 94, 104, 115
ISP1761
PLL 30 MHz SEL16/32 60 MHz
11 12 13
XTAL1 XTAL2 CLKIN
BUS INTERFACE: MEMORY MANAGEMENT UNIT + SLAVE DMA CONTROLLER + INTERRUPT CONTROL MEMORY ARBITER AND FIFO POWER-ON RESET AND VBAT ON HC BUFFER MEMORY 64 KBYTES DC BUFFER MEMORY 8 KBYTES GLOBAL CONTROL AND POWER MANAGEMENT
122 119 120
C_A VCC(C_IN)
Fig 1. Block diagram
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Product data sheet
GENERIC PROCESSOR BUS
17 CS_N RD_N WR_N DC_IRQ HC_IRQ DC_DREQ HC_DREQ HC_DACK DC_DACK
RESET_N HC_SUSPEND/ WAKEUP_N DC_SUSPEND/ WAKEUP_N
110
VBAT_ON_N
REGISTERS SUPPORT 124 125 126 CHARGE PUMP TRANSACTION TRANSLATOR (TT) AND RAM ADVANCED PHILIPS SLAVE HOST CONTROLLER ADVANCED PERIPHERAL CONTROLLER
5, 50, 85, 118 5 V-TO-1.8 V VOLTAGE REGULATOR 6, 7
VREG(1V8) VCC(5V0)
C_B
5 V-TO-3.3 V VOLTAGE REGULATOR
9
VREG(3V3)
OTG CONTROLLER DYNAMIC PORT ROUTING AND PORT CONTROL LOGIC
DIGITAL AND ANALOG 2 OVERCURRENT PROTECTION 3
REF5V
ID
HI-SPEED USB ATX1
HI-SPEED USB ATX2
HI-SPEED USB ATX3
16 15 20 19 18 RREF1 DP1 GND
21 127
23 22 27 26 25 DP2 DM2
28 128 30 29 34 33 32 35 1 DM3 OC3_N PSW3_N
4, 8, 14, 17, 24, 31, 36, 44, 53, 55, 63, 71, 79, 88, 90, 99, 109, 121, 123
004aaa450
DM1
RREF2 OC1_N/ VBUS
RREF3
DP3
GND
GND
GND
GND
OC2_N GND PSW2_N
GND
PSW1_N
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Rev. 01 -- 12 January 2005
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Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
6. Pinning information
6.1 Pinning
128 103 102
1
ISP1761BE
38 39 64 4 3 5 6 7 8 9 10 11
65
004aaa506
Fig 2. Pin configuration (LQFP128); top view
ball A1 index area 1 A B C D E F G H J K L M N P R T
2
12 13
14 15
16
ISP1761ET
004aaa551
Fig 3. Pin configuration (TFBGA128); top view
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Product data sheet
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ISP1761
Hi-Speed USB OTG controller
6.2 Pin description
Table 2: Symbol [1] OC3_N Pin description Pin LQFP128 1 Ball Type [2] TFBGA128 C2 AI/I Description port 3 analog (5 V input) and digital overcurrent input; if not used, connect to VCC(I/O) through a 10 k resistor input, 3.3 V tolerant REF5V ID 2 3 A2 B2 AI I 5 V reference input for analog OC detector; connect a 100 nF decoupling capacitor ID input for detection of the default host or peripheral setting when port 1 is in the OTG mode input, 3.3 V tolerant GND VREG(1V8) 4 5 A1 B1 P analog ground core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor; for details on additional capacitor placement, see Section 7.7 input to internal regulators (3.0 V to 5.5 V); connect a 100 nF decoupling capacitor; see Section 7.7 input to internal regulators (3.0 V to 5.5 V); connect a 100 nF decoupling capacitor; see Section 7.7 oscillator ground regulator output (3.3 V); for decoupling only; connect a 100 nF capacitor and a 4.7 F to 10 F capacitor; see Section 7.7 digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 12 MHz crystal connection input; connect to ground if an external clock is used 12 MHz crystal connection output 12 MHz oscillator or clock input; connect to VCC(I/O) when not in use 3.3 V tolerant GND GND RREF1 GND DM1 GND DP1 PSW1_N GND RREF2 GND DM2 GND
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VCC(5V0) VCC(5V0) GND VREG(3V3) VCC(I/O) XTAL1 XTAL2 CLKIN
6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
C1 D2 E3 D1 E2 E1 F2 F1 G3 G2 G1 H2 H1 J3 J2 J1 K2 K1 L3 L1 L2
P P P P AI AO I AI AI/O AI/O OD AI AI/O -
digital ground RREF1 ground reference resistor connection; connect a 12 k 1 % resistor between this pin and the RREF1 ground analog ground for port 1 downstream data minus port 1 analog ground downstream data plus port 1 power switch port 1, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant RREF2 ground reference resistor connection; connect a 12 k 1 % resistor between this pin and the RREF2 ground analog ground for port 2 downstream data minus port 2 analog ground
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ISP1761
Hi-Speed USB OTG controller
Table 2: Symbol [1] DP2 PSW2_N GND RREF3 GND DM3 GND DP3 PSW3_N GND DATA0
Pin description...continued Pin LQFP128 27 28 29 30 31 32 33 34 35 36 37 Ball Type [2] TFBGA128 M2 M1 N2 N1 P2 P1 R2 R1 T1 T2 R3 AI/O OD AI AI/O AI/O OD I/O Description downstream data plus port 2 power switch port 2, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant RREF3 ground reference resistor connection; connect a 12 k 1 % resistor between this pin and the RREF3 ground analog ground for port 3 downstream data minus port 3 analog ground downstream data plus port 3 power switch port 3, active LOW output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant digital ground data bit 0 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA1
38
T3
I/O
data bit 1 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA2
39
R4
I/O
data bit 2 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA3
40 41
T4 P5
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 data bit 3 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA4
42
T5
I/O
data bit 4 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA5
43
R5
I/O
data bit 5 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA6
44 45
T6 R6
I/O
digital ground data bit 6 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA7
46
P7
I/O
data bit 7 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA8
47
T7
I/O
data bit 8 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
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ISP1761
Hi-Speed USB OTG controller
Table 2: Symbol [1] VCC(I/O) DATA9
Pin description...continued Pin LQFP128 48 49 Ball Type [2] TFBGA128 R7 T8 P I/O Description digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 data bit 9 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VREG(1V8)
50
R8
P
core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor; for details on additional capacitor placement, see Section 7.7 data bit 10 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA10
51
P9
I/O
DATA11
52
T9
I/O
data bit 11 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA12
53 54
R9 T10
I/O
core ground data bit 12 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA13
55 56
R10 P11
I/O
digital ground data bit 13 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA14
57
T11
I/O
data bit 14 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA15
58
R11
I/O
data bit 15 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA16
59 60
T12 R12
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 data bit 16 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA17
61
T13
I/O
data bit 17 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA18
62
R13
I/O
data bit 18 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA19
63 64
R14 T14
I/O
digital ground data bit 19 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
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Product data sheet
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ISP1761
Hi-Speed USB OTG controller
Table 2: Symbol [1] DATA20
Pin description...continued Pin LQFP128 65 Ball Type [2] TFBGA128 T15 I/O Description data bit 20 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA21
66
R15
I/O
data bit 21 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA22
67 68
P15 T16
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 data bit 22 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA23
69
R16
I/O
data bit 23 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA24
70
P16
I/O
data bit 24 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA25
71 72
N16 N15
I/O
digital ground data bit 25 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA26
73
M15
I/O
data bit 26 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA27
74
M16
I/O
data bit 27 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
VCC(I/O) DATA28
75 76
M14 L16
P I/O
digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 data bit 28 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA29
77
L15
I/O
data bit 29 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
DATA30
78
K16
I/O
data bit 30 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
GND DATA31
79 80
K15 K14
I/O
digital ground data bit 31 input and output bidirectional pad, push-pull input, three-state output, 4 mA output drive, 3.3 V tolerant
TEST A1
81 82
J16 H16
I
connect to ground address pin 1 input, 3.3 V tolerant
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ISP1761
Hi-Speed USB OTG controller
Table 2: Symbol [1] VCC(I/O) A2 VREG(1V8)
Pin description...continued Pin LQFP128 83 84 85 Ball Type [2] TFBGA128 J15 H15 G16 P I P Description digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 address pin 2 input, 3.3 V tolerant core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor and a 4.7 F to 10 F capacitor; see Section 7.7 address pin 3 input, 3.3 V tolerant address pin 4 input, 3.3 V tolerant core ground address pin 5 input, 3.3 V tolerant digital ground address pin 6 input, 3.3 V tolerant address pin 7 input, 3.3 V tolerant address pin 8 input, 3.3 V tolerant digital supply; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 address pin 9 input, 3.3 V tolerant address pin 10 input, 3.3 V tolerant address pin 11 input, 3.3 V tolerant address pin 12 input, 3.3 V tolerant digital ground address pin 13 input, 3.3 V tolerant address pin 14 input, 3.3 V tolerant address pin 15 input, 3.3 V tolerant address pin 16 input, 3.3 V tolerant digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7
A3 A4 GND A5 GND A6 A7 A8 VCC(I/O) A9 A10 A11 A12 GND A13 A14 A15 A16 VCC(I/O)
86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
H14 F16 G15 F15 E16 F14 E15 D16 D15 C16 C15 B16 B15 A16 A15 B14 A14 A13 B13
I I I I I I P I I I I I I I I P
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ISP1761
Hi-Speed USB OTG controller
Table 2: Symbol [1] A17 CS_N
Pin description...continued Pin LQFP128 105 106 Ball Type [2] TFBGA128 C12 A12 I I Description address pin 17 input, 3.3 V tolerant chip select signal that indicates the area being accessed; active LOW input, 3.3 V tolerant read enable; active LOW input, 3.3 V tolerant write enable; active LOW input, 3.3 V tolerant digital ground to indicate the presence of a minimum 3.3 V on pins 6 and 7 (open-drain); connect to VCC(I/O) through a 10 k pull-up resistor output pad, push-pull open-drain, 8 mA output drive, 5 V tolerant Peripheral Controller interrupt signal output 4 mA drive, 3.3 V tolerant Host Controller interrupt signal output 4 mA drive, 3.3 V tolerant DMAC request for the Peripheral Controller output 4 mA drive, 3.3 V tolerant DMAC request for Host Controller output 4 mA drive, 3.3 V tolerant digital voltage; 1.65 V to 3.6 V; connect a 100 nF decoupling capacitor; see Section 7.7 Host Controller DMA request acknowledgment; when not in use, connect to VCC(I/O) through a 10 k pull-up resistor input, 3.3 V tolerant Peripheral Controller DMA request acknowledgment; when not in use, connect to VCC(I/O) through a 10 k pull-up resistor input, 3.3 V tolerant core power output (1.8 V); internal 1.8 V for the digital core; used for decoupling; connect a 100 nF capacitor; for details on additional capacitor placement, see Section 7.7 Host Controller suspend and wake-up; three-state suspend output (active LOW) and wake-up input circuits are connected together
RD_N WR_N GND VBAT_ON_N
107 108 109 110
B12 B11 A11 C10
I I OD
DC_IRQ HC_IRQ DC_DREQ HC_DREQ VCC(I/O) HC_DACK
111 112 113 114 115 116
A10 B10 A9 B9 C8 A8
O O O O P I
DC_DACK
117
B8
I
VREG(1V8)
118
B7
P
HC_SUSPEND 119 /WAKEUP_N
A7
I/OD
* *
HIGH = output is three-state; ISP1761 is in suspend mode LOW = output is LOW; ISP1761 is not in suspend mode.
connect to VCC(I/O) through an external 10 k pull-up resistor output pad, open-drain, 4 mA output drive, 3.3 V tolerant
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ISP1761
Hi-Speed USB OTG controller
Table 2: Symbol [1]
Pin description...continued Pin LQFP128 Ball Type [2] TFBGA128 C6 I/OD Description Peripheral Controller suspend and wake-up; three-state suspend output (active LOW) and wake-up input circuits are connected together
DC_SUSPEND 120 /WAKEUP_N
* *
HIGH = output is three-state; ISP1761 is in suspend mode LOW = output is LOW; ISP1761 is not in suspend mode.
connect to VCC(I/O) through an external 10 k pull-up resistor output pad, open-drain, 4 mA output drive, 3.3 V tolerant GND RESET_N 121 122 A6 B6 I core ground external power-up reset; active LOW input, 3.3 V tolerant Remark: During reset, ensure that all the input pins to the ISP1761 are not toggling. GND C_B C_A VCC(C_IN) OC1_N/VBUS 123 124 125 126 127 B5 A5 B4 A4 B3 AI/O AI/O P (AI/O)(I) analog ground charge pump capacitor input; connect a 220 nF capacitor between this pin and pin 125 charge pump capacitor input; connect a 220 nF capacitor between this pin and pin 124 charge pump input; connect to 3.3 V This pin has multiple functions:
* * *
Port 1 OC1_N detection when port 1 is configured for host functionality and an external power switch is used; connect to VCC(I/O) through a 10 k resistor VBUS out when internal charge pump is used and port 1 is configured for the host functionality; maximum 50 mA current capability; only for port 1 VBUS input detection when port 1 is defined for the peripheral functionality.
input, 3.3 V tolerant OC2_N 128 A3 AI/I port 2 analog (5 V input) and digital overcurrent input; if not used, connect to VCC(I/O) through a 10 k resistor input, 3.3 V tolerant
[1] [2] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. I = input only; O = output only; I/O = digital input/output; OD = open-drain output; AI/O = analog input/output; AI = analog input; P = power; (AI/O)(I) = analog input/output digital input; AI/I = analog input digital input.
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Product data sheet
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ISP1761
Hi-Speed USB OTG controller
7. Functional description
7.1 ISP1761 internal architecture: Advanced Philips Slave Host Controller and hub
The EHCI block and the Hi-Speed USB hub block are the main components of the Advanced Philips Slave Host Controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1761 is adapted from Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. The internal Hi-Speed USB hub block replaces the companion Host Controller block used in the original architecture of a Peripheral Component Interconnect (PCI) Hi-Speed USB Host Controller to handle the full-speed and low-speed modes. The hardware architecture in the ISP1761 is simplified to help reduce cost and development time, by eliminating the additional work involved in implementing the OHCI software required to support the full-speed and low-speed modes. Figure 4 shows the internal architecture of the ISP1761. The ISP1761 implements an EHCI that has an internal port--the Root Hub port (not available externally)--on which the internal hub is connected. The three external ports are always routed to the internal hub. The internal hub is a Hi-Speed USB hub including the TT. Remark: The root hub must be enabled and the internal hub must be enumerated. Enumerate the internal hub as if it is externally connected. For details, refer to ISP176x Linux Programming Guide (AN10042). At the Host Controller reset and initialization, the internal Root Hub port will be polled until a new connection is detected, showing the connection of the internal hub. The internal Hi-Speed USB hub is enumerated using a sequence similar to a standard Hi-Speed USB hub enumeration sequence, and the polling on the Root Hub is stopped because the internal Hi-Speed USB hub will never be disconnected. When enumerated, the internal hub will report the three externally available ports.
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EHCI ROOT HUB PORTSC1
ENUMERATION AND POLLING USING ACTUAL PTDs
INTERNAL HUB (TT)
PORT1
PORT2
PORT3
EXTERNAL PORTS
004aaa513
Fig 4. Internal hub
7.1.1 Internal clock scheme
Figure 5 shows the internal clock scheme of the ISP1761. The ISP1761 has three ports.
DIGITAL CORE host clock: 48 MHz, 30 MHz, 60 MHz
PORT 2 ATX
HOST CORE
XOSC
peripheral clock: 48 MHz, 30 MHz, 60 MHz PORT 1 ATX
PERIPHERAL CORE
004aaa538
PLL 12 MHz IN
PORT 3 ATX
Fig 5. ISP1761 clock scheme
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Port 2 does not need to be enabled using software if only port 1 or port 3 is used. No port needs to be disabled by external pull-up resistors, if not used. The DP and DM of the unused ports need not be externally pulled HIGH because there are internal pull-down resistors on each port that are enabled by default. Table 3 lists the various port connection scenarios.
Table 3: Port connection scenarios Port 2 DP and DM are not connected (left open) DP and DM are routed to USB connector DP and DM are not connected (left open) DP and DM are routed to USB connector DP and DM are routed to USB connector DP and DM are not connected (left open) DP and DM are routed to USB connector Port 3 DP and DM are not connected (left open) DP and DM are not connected (left open) DP and DM are routed to USB connector DP and DM are not connected (left open) DP and DM are routed to USB connector DP and DM are routed to USB connector DP and DM are routed to USB connector DP and DM are routed to USB connector DP and DM are not connected (left open) DP and DM are not connected (left open) DP and DM are routed to USB connector DP and DM are not connected (left open) DP and DM are routed to USB connector DP and DM are routed to USB connector
Port configuration Port 1 One port (port 1) One port (port 2) One port (port 3) Two ports (ports 1 and 2) Two ports (ports 2 and 3) Two ports (ports 1 and 3) Three ports (ports 1, 2 and 3)
7.2 Host Controller buffer memory block
7.2.1 General considerations
The internal addressable Host Controller buffer memory is 63 kB. The 63 kB effective memory size is the result of subtracting the size of registers (1 kB) from the total addressable memory space defined by the ISP1761 (64 kB). This is an optimized value for achieving the highest performance with a minimal cost. The ISP1761 is a slave Host Controller. This means that it does not need access to the local bus of the system to transfer data from the memory of the system to the ISP1761 internal memory, unlike the case of the original PCI Hi-Speed USB Host Controllers. Therefore, correct data must be transferred to both the Philips Transfer Descriptor (PTD) area and the payload area by Parallel I/O (PIO) (CPU access) or programmed DMA. The `slave-host' architecture ensures better compatibility with most of the processors present in the market today because not all processors allow a `bus-master' on the local bus. It also allows better load balancing of the processor's local bus because only the internal bus arbiter of the processor controls the transfer of data dedicated to USB. This prevents the local bus from being busy when other more important transfers may be in the queue; and therefore achieving a `linear' system data flow that has less impact on other processes running at the same time. The considerations mentioned are also the main reason for implementing the prefetching technique, instead of using a READY signal. The resulting architecture avoids `freezing' of the local bus (by asserting READY), enhancing the ISP1761 memory access time, and avoiding introduction of programmed additional wait states. For details, see Section 7.3.
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The total amount of memory allocated to the payload determines the maximum transfer size specified by a PTD--a bigger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage. A larger buffer also implies a larger amount of data can be transferred. This transfer, however, can be done over a longer period of time, to maintain the overall system performance. Each transfer of the USB data on the USB bus can span up to a few milliseconds before requiring further CPU intervention for data movement. The internal architecture of the ISP1761 allows a flexible definition of the memory buffer for optimization of the data transfer on the CPU extension bus and the USB. It is possible to implement different data transfer schemes, depending on the number and type of USB devices present (for example: push-pull--data can be written to half of the memory while data in the other half is being accessed by the Host Controller and sent on the USB bus). This is useful especially when a high-bandwidth `continuous or periodic' data flow is required. Through an analysis of the hardware and software environment regarding the usual data flow and performance requirements of most embedded systems, Philips has determined the optimal size for the internal buffer as approximately 64 kB.
7.2.2 Structure of the ISP1761 Host Controller memory
The 63 kB of internal memory consists of the PTD area and the payload area. Both the PTD and payload memory zones are divided into three dedicated areas for each main type of USB transfer: isochronous (ISO), interrupt (INT) and Acknowledged Transfer List (ATL). As shown in Table 4, the PTD areas for ISO, INT and ATL are grouped at the beginning of the memory, occupying the address range 0400h to 0FFFh, following the address space of the registers. The payload or data area occupies the next memory address range 1000h to FFFFh, meaning that 60 kB of memory are allocated for the payload data. A maximum of 32 PTD areas and their allocated payload areas can be defined for each type of transfer. The structure of a PTD is similar for every transfer type and consists of eight Double Words (DWs) that must be correctly programmed for a correct USB data transfer. The reserved bits of a PTD must be set to logic 0. A detailed description of the PTD structure can be found in Section 8.5. The transfer size specified by the PTD determines the contiguous USB data transfer that can be performed without any CPU intervention. The respective payload memory area must be equal to the transfer size defined. The maximum transfer size is flexible and can be optimized, depending on the number and nature of USB devices or PTDs defined and their respective MaxPacketSize. The CPU will program the DMA to transfer the necessary data in the payload memory. The next CPU intervention will be required only when the current transfer is completed and DMA programming is necessary to transfer the next data payload. This is normally signaled by the IRQ that is generated by the ISP1761 on completing the current PTD, meaning all the data in the payload area was sent on the USB bus. The external IRQ signal is asserted according to the settings in the IRQ Mask OR or IRQ MASK AND registers, see Section 8.4.
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The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping or delaying any other USB transaction or corrupting the RAM data. Some of the design features are:
* The address range of the internal RAM buffer is from 0400h to FFFFh. * The internal memory contains isochronous, interrupt and asynchronous PTDs, and
respective defined payloads.
* All accesses to the internal memory are double-word aligned. * Internal memory address range calculation:
Memory address = (CPU address - 0400h) (shift right >> 3). Base address is 0400h.
Table 4: ISO INT ATL Payload Memory address CPU address 0400h to 07FFh 0800h to 0BFFh 0C00h to 0FFFh 1000h to FFFFh Memory address 0000h to 007Fh 0080h to 00FFh 0100h to 017Fh 0180h to 1FFFh
Memory map
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63 kbytes
PTD1 PTD2 ISOCHRONOUS .. PTD32 PTD1 PTD2 .. INTERRUPT PTD32 PTD1 PTD2 .. REGISTERS ASYNC
PTD32 PAYLOAD
D[15:0]/D[31:0] A[17:1]
........
USB BUS
USB HIGH-SPEED HOST AND TRANSACTION TRANSLATOR (FULL-SPEED AND LOW-SPEED)
PAYLOAD
PAYLOAD address data (64 bits)
240 MB/s
MEMORY MAPPED INPUT/OUTPUT, MEMORY MANAGEMENT UNIT, SLAVE DMA CONTROLLER AND INTERRUPT CONTROL
CS_N RD_N WR_N DC_IRQ HC_IRQ DC_DREQ HC_DREQ MICROPROCESSOR
ARBITER HC_DACK DC_DACK control signals
004aaa568
Fig 6. Memory segmentation and access block diagram
Both the CPU interface logic and the USB Host Controller require access to the internal ISP1761 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s. This bandwidth avoids any bottleneck on accesses both from the CPU interface and the internal USB Host Controller.
7.3 Accessing the ISP1761 Host Controller memory: PIO and DMA
The CPU interface of the ISP1761 can be configured for a 16-bit or 32-bit data bus width. When the ISP1761 is configured for a 16-bit data bus width, the upper unused 16 data lines must be pulled up to VCC(I/O). This can be achieved by connecting DATA[31:16] lines together to a single 10 k pull-up resistor. The 16-bit or 32-bit data bus width configuration is done by programming bit 8 of the HW Mode Control register. This will determine the register and memory access types in both PIO and DMA modes to all internal blocks: Host Controller, Peripheral Controller and OTG Controller. All accesses must be word-aligned for 16-bit mode and double-word aligned for 32-bit mode, where one word = 16 bits. When accessing the Host Controller registers in 16-bit mode, the
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register access must always be completed using two subsequent accesses. In the case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number of bursts that will complete a certain transfer length. In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA mode, the data validation is performed by DACK--instead of CS_N--together with the WR_N and RD_N signals. The DREQ signal will always be asserted as soon as the ISP1761 DMA is enabled, as described in the following section.
7.3.1 PIO mode access--memory read cycle
The following method has been implemented to reduce the read access timing in the case of a memory read:
* The Memory register contains the starting address and the bank selection to read
from the memory. Before every new read cycle of the same or different banks, an appropriate value is written to this register.
* Once a value is written to this register, the address is stored in the FIFO of that bank
and is then used to prefetch data for the memory read of that bank. For every subsequent read operation executed at a contiguous address, the address pointer corresponding to that bank is automatically incremented to prefetch the next data to be sent to the CPU. Memory read accesses for multiple banks can be interleaved. In this case, the FIFO block handles the MUXing of appropriate data to the CPU.
* The address written to the Memory register is incremented and used to successively
prefetch data from the memory irrespective of the value on the address bus for each bank, until a new value for a bank is written to the Memory register. For example, consider the following sequence of operations: - Write the starting (read) address 4000h and bank1 = 01 to the Memory register. When RD_N is asserted for three cycles with A[17:16] = 01, the returned data corresponds to addresses 4000h, 4004h and 4008h. Remark: Once 4000h is written to the Memory register for bank1, the bank select value determines the successive incremental addresses used to fetch the data. That is, the fetching of data is independent of the address on A[15:0] lines. - Write the starting (read) address 4100h and bank2 = 10 to the Memory register. When RD_N is asserted for four cycles with A[17:16] = 10, the returned data corresponds to addresses 4100h, 4104h, 4108h and 410Ch. Consequently, the RD_N assertion with A[17:16] = 01 will return data from 400Ch because the bank1 read stopped there in the previous cycle. Also, RD_N assertions with A[17:16] = 10 will now return data from 4110h because the bank2 read stopped there in the previous cycle.
7.3.2 PIO mode access--memory write cycle
The PIO memory write access is similar to a normal memory access. It is not necessary to set the prefetching address before a write cycle to memory. The ISP1761 internal write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The memory write address must be incremented before every access.
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7.3.3 PIO mode access--register read cycle
The PIO register read access is similar to a general register access. It is not necessary to set a prefetching address before a register read. The ISP1761 register read address will not be automatically incremented during consecutive read accesses, unlike in a series of ISP1761 memory read cycles. The ISP1761 register read address must be correctly specified before every access.
7.3.4 PIO mode access--register write cycle
The PIO register write access is similar to a general register access. It is not necessary to set a prefetching address before a register write. The ISP1761 register write address will not be automatically incremented during consecutive write accesses, unlike in a series of ISP1761 memory read cycles. The ISP1761 register write address must be correctly specified before every access.
7.3.5 DMA--read and write operations
The internal ISP1761 Host Controller DMA is a slave DMA. The host system processor or DMA must ensure the data transfer to or from the ISP1761 memory. The ISP1761 DMA supports a DMA burst length of 1, 4, 8 and 16 cycles for both the 16-bit and 32-bit data bus width. DREQ will be asserted at the beginning of the first burst of a DMA transfer and will be deasserted on the last cycle (RD_N or WR_N active pulse) of that burst. It will be reasserted shortly after the DACK deassertion, as long as the DMA transfer counter was not reached. DREQ will be deasserted on the last cycle when the DMA transfer counter is reached and will not reasserted until the DMA reprogramming is performed. Both the DREQ and DACK signals are programmable as active LOW or active HIGH, according to the system requirements. The DMA start address must be initialized in the respective register, and the subsequent transfers will automatically increment the internal ISP1761 memory address. A register or memory access or access to other system memory can occur in between DMA bursts, whenever the bus is released because DACK is deasserted, without affecting the DMA transfer counter or the current address. Any memory area can be accessed by the system's DMA at any starting address because there are no predefined memory blocks. The DMA transfer must start on a word or Double Word address, depending on whether the data bus width is set to 16-bit or 32-bit. DMA is the most efficient method to initialize the payload area, to reduce the CPU usage and overall system loading. The ISP1761 does not implement EOT to signal the end of a DMA transfer. If programmed, an interrupt may be generated by the ISP1761 at the end of the DMA transfer. The slave DMA of the ISP1761 will issue a DREQ to the DMA controller of the system to indicate that it is programmed for transfer and data is ready. The system DMA controller may also start a transfer without the need of the DREQ, if the ISP1761 memory is available for the data transfer and the ISP1761 DMA programming is completed.
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It is also possible that the system's DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1761 memory. The ISP1761 will be accessed in the PIO mode. Consequently, memory read operations must be preceded by initializing the Memory register (address 033Ch), as described in Section 7.3.1. No IRQ will be generated by the ISP1761 on completing the DMA transfer but an internal processor interrupt may be generated to signal that the DMA transfer is completed. This is mainly useful in implementing the double-buffering scheme for data transfer to optimize the USB bandwidth. The ISP1761 DMA programming involves:
* Set the active levels of signals DREQ and DACK in the HW Mode Control register. * The DMA Start Address register contains the first memory address at which the data
transfer will start. It must be word-aligned in the 16-bit data bus mode and double word aligned in the 32-bit data bus mode.
* The programming of the HcDMAConfiguration register specifies:
- The type of transfer that will be performed: read or write. - The burst size--expressed in bytes--is specified, regardless of the data bus width. For the same burst size, a double number of cycles will be generated in the 16-bit mode data bus width as compared to the 32-bit mode. - The transfer length--expressed in number of bytes--defines the number of bursts. The DREQ will be deasserted and asserted to generate the next burst, as long as there are bytes to be transferred. At the end of a transfer, the DREQ will be deasserted and an IRQ can be generated if DMAEOTINT (bit 3 in the HcInterrupt register) is set. The maximum DMA transfer size is equal to the maximum memory size. The transfer size can be an odd or even number of bytes, as required. If the transfer size is an odd number of bytes, the number of bytes transferred by the system's DMA is equal to the next multiple of two for the 16-bit data bus width or four for the 32-bit data bus width. For a write operation, however, only the specified odd number of bytes in the ISP1761 memory will be affected. - Enable ENABLE_DMA (bit 1) of the HcDMAConfiguration register to determine the assertion of DREQ immediately after setting the bit. After programming the preceding parameters, the system's DMA may be enabled (waiting for the DREQ to start the transfer or immediate transfer may be started). The programming of the system's DMA must match the ISP1761 DMA parameters programmed above. Only one DMA transfer may take place at a time. A PIO mode data transfer may occur simultaneously with a DMA data transfer, in the same or a different memory area.
7.4 Interrupts
The ISP1761 will assert the IRQ according to the source or event in the HcInterrupt register. The main steps to enable the IRQ assertion are: 1. Set GLOBAL_INTR_EN (bit 0) in the HW Mode Control register. 2. Define the IRQ active as level or edge in INTR_LEVEL (bit 1) of the HW Mode Control register.
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3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match the IRQ settings of the host processor. By default, interrupt is level-triggered and active LOW. 4. Program the individual Interrupt Enable bits in the HcInterruptEnable register. The software will need to clear the Interrupt status bits in the HcInterrupt register before enabling individual interrupt enable bits. Additional IRQ characteristics can be adjusted in the Edge Interrupt Count register, as necessary, applicable only when IRQ is set to be edge-active (a pulse of a defined width is generated every time the IRQ is active). Bits 15 to 0 of the Edge Interrupt Count register define the IRQ pulse width. The maximum pulse width that can be programmed is FFFFh, corresponding to a 1 ms pulse width. This setting is necessary for certain processors that may require a different minimum IRQ pulse width than the default value. The default IRQ pulse width set at power on is approximately 500 ns. Bits 31 to 24 of the Edge Interrupt Count register define the minimum interval between two interrupts to avoid frequent interrupts to the CPU. The default value of 00h attributed to these bits determines the normal IRQ generation, without any delay. When a delay is programmed and the IRQ becomes active after the respective delay, several IRQ events may have already occurred. All the interrupt events are represented by the respective bits allocated in the HcInterrupt register. There is no mechanism to show the order or the moment occurrence of an interrupt. The asserted bits in the HcInterrupt register can be cleared by writing back the same value to the HcInterrupt register. This means that writing logic 1 to each of the set bits will reset that corresponding bits to the initial inactive state. The IRQ generation rules that apply according to the preceding settings are:
* If an event of interrupt occurs but the respective bit in the Interrupt Enable register is
not set, then the respective HcInterrupt register bit is set but the interrupt signal is not asserted. An interrupt will be generated when interrupt is enabled and the respective bit in the Interrupt Enable register is set.
* For a level trigger, an interrupt signal remains asserted until the processor clears the
HcInterrupt register by writing logic 1 to clear the HcInterrupt register bits that are set.
* If an interrupt is made edge-sensitive and is asserted, writing to clear the HcInterrupt
register will not have any effect because the interrupt will be asserted for a prescribed amount of clock cycles.
* The clock stopping mechanism does not affect the generation of an interrupt. This is
useful during the suspend and resume cycles, when an interrupt is generated to signal a wake-up event. The IRQ generation can also be conditioned by programming the IRQ Mask OR and IRQ Mask AND registers. Setting some of the bits in these registers to logic 1 will determine the IRQ generation only when the respective AND or OR conditions of completing the respective PTDs is met.
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With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer-- ISO, INT and bulk--software can determine which PTDs get priority and an interrupt will be generated when the AND or OR conditions are met. The PTDs that are set will wait until the respective bits of the remaining PTDs are set and then all PTDs generate an interrupt request to the CPU together. The registers definition shows that the AND or OR conditions are applicable to the same category of PTDs--ISO, INT and ATL. When an IRQ is generated, the PTD Done Map registers and the respective V bits will show which PTDs were completed. The rules that apply to the IRQ Mask AND or IRQ Mask OR settings are:
* The OR mask has a higher priority over the AND mask. An IRQ is generated if bit n of
done map is set and the corresponding bit n of the OR mask register is set.
* If the OR mask for any done bit is not set, then the AND mask comes into picture. An
IRQ is generated if all the corresponding done bits of the AND Mask register are set. For example: If bits 2, 4 and 10 are set in the AND Mask register, an IRQ is generated only if bits 2, 4, 10 of the done map are set.
* If using the IRQ interval setting for the bulk PTD, an interrupt will only occur at the
regular time interval as programmed in the ATL Done Timeout register. Even if an interrupt event occurs before the timeout of the register, no IRQ will be generated until the time is up. For an example on using the IRQ Mask AND or IRQ Mask OR registers, without the ATL Done Timeout register, see Table 5. The AND function: activate the IRQ only if PTDs 1, 2 and 4 are done. The OR function: if any of the PTDs 7, 8 or 9 are done, an IRQ for each of the PTD will be raised.
Table 5: PTD 1 2 3 4 5 6 7 8 9 1 1 0 1 0 0 0 0 0 Using the IRQ Mask AND or IRQ Mask OR registers AND register OR register 0 0 0 0 0 0 1 1 1 Time 1 ms 3 ms 5 ms 6 ms 7 ms PTD done 1 1 1 1 1 1 IRQ active because of AND active because of OR active because of OR active because of OR
7.5 Phase-Locked Loop (PLL) clock multiplier
The internal PLL requires a 12 MHz input, which can be a 12 MHz crystal or a 12 MHz clock already existing in the system with a precision better than 50 ppm. This allows the use of a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI). When an external crystal is used, make sure the CLKIN pin is connected to VCC(I/O).
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The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz. No external components are required for the PLL operation.
7.6 Power management
The ISP1761 implements a flexible power management scheme, allowing various power saving stages. The usual powering scheme implies programming EHCI registers and the internal Hi-Speed USB (USB 2.0) hub in the same way it is done in the case of a PCI Hi-Speed USB Host Controller with a Hi-Speed USB hub attached. While the ISP1761 is set in suspend mode, the main internal clocks will be stopped to ensure minimum power consumption. An internal LazyClock of 100 kHz 40 % will continue running. This allows initiating a resume on one of the following events:
* External USB device connect or disconnect * Assertion of the CS_N signal because of any access to the ISP1761 * Driving the HC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the
Host Controller, and driving the DC_SUSPEND/WAKEUP_N pin to a LOW logical level will wake up the Peripheral Controller The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are bidirectional. These pins should be connected to the GPIO pins of a processor. The awake state can be verified by reading the LOW level of this pin. If the level is HIGH, it means that the ISP1761 is in the suspend state. HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N require pull-up resistors because in the ISP1761 suspended state these pins become three-state and can be pulled down, driving them externally by switching the processor's GPIO lines to the output mode to generate the ISP1761 wake-up. The HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins are three-state output and also input to the internal wake-up logic. When in suspend mode, the ISP1761 internal wake-up circuitry will sense the status of the HC_SUSPEND/WAKEUP_N and DC_SUSPEND/WAKEUP_N pins:
* If the pins remain pulled-up, no wake-up will be generated because a HIGH is sensed
by the internal wake-up circuit.
* If the pins are externally pulled LOW (for example, by the GPIO lines or just a test by
jumpers), the input to the wake-up circuitry becomes LOW and the wake-up is internally initiated. The resume state has a clock-off count timer defined by bits 31 to 16 of the Power Down Control register. The default value of this timer is 10 ms, meaning that the resume state will be maintained for 10 ms. If during this time, the RUN/STOP bit in the USBCMD register is set to logic 1, the Host Controller will go into a permanent resume--the normal functional state. If the RUN/STOP bit is not set during the time determined by the clock-off
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count, the ISP1761 will switch back to suspend mode after the specified time. The maximum delay that can be programmed in the clock-off count field is approximately 500 ms. Additionally, the Power Down Control register allows the ISP1761 internal blocks to disable for lower power consumption as defined in Table 8. The lowest suspend current (ICC(susp)) that can be achieved is approximately 150 A at room temperature. The suspend current will increase with the increase in temperature, with approximately 300 A at 40 C and up to a typical 1 mA at 85 C. The system is not in suspend mode when its temperature increases above 40 C. Therefore, even a 1 mA current consumption by the ISP1761 in suspend mode can be considered negligible. In normal environmental conditions, when the system is in suspend mode, the maximum ISP1761 temperature is approximately 40 C, determined by the ambient temperature. Therefore, the ISP1761 maximum suspend current will be below 300 A. An alternative solution to achieve a very low suspend current is to completely switch off the VCC(5V0) power input by using an external PMOS transistor, controlled by one of the GPIO pins of the processor. This is possible because the ISP1761 can be used in the hybrid mode, which allows only the VCC(I/O) powered on to avoid loading of the system bus. The time from wake-up to suspend will be approximately 100 ms when the ISP1761 power is always on. It is necessary to wait for the CLK_RDY interrupt assertion before programming the ISP1761 because internal clocks are stopped during deep sleep suspend and restarted after the first wake-up event. The occurrence of the CLK_RDY interrupt means that the internal clocks are running and the normal functionality is achieved. It is estimated that the CLK_RDY interrupt will be generated less than 100 s after the wake-up event, if the power to the ISP1761 was on during suspend. If the ISP1761 is used in the hybrid mode and VCC(5V0) is off during suspend, a 2 ms reset pulse is required when the power is switched back to on, before starting to program the resume state. This will ensure that the internal clocks are running and all logics reach a stable initial state.
7.7 Power supply
Figure 7 shows the ISP1761 power supply connection.
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6, 7
VCC(5V0)
3.3 V to 5 V
100 nF
10, 40, 48, 59, 67, 75, 83, 94, 104, 115 85
VCC(I/O)
1.65 V to 3.6 V
100 nF
VREG(1V8) +
10 F
ISP1761
VREG(1V8) 5, 50, 118
100 nF
100 nF
VREG(3V3) 9
10 F
+
100 nF
126
004aaa539
VCC(C_IN)
3.3 V
100 nF
A 4.7 F to 10 F capacitor is required on any one of the pins--5, 50 and 118.
Fig 7. ISP1761 power supply connection
Figure 8 shows the most commonly used power supply connection.
ISP1761
6, 7, 10, 40, 48, 59, 67, 75, 83, 94, 104, 115, 126 VCC(5V0), VCC(I/O), VCC(C_IN)
100 nF
3.3 V
85
VREG(1V8)
10 F 100 nF
VREG(1V8) 5, 50, 118
100 nF
VREG(3V3) 9
10 F 100 nF
004aaa540
A 4.7 F to 10 F capacitor is required on any one of the pins--5, 50 and 118.
Fig 8. Most commonly used power supply connection
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7.7.1 Hybrid mode
Table 6 shows the description of hybrid mode.
Table 6: Voltage VCC(5V0) VCC(I/O) Hybrid mode Status off on
In hybrid mode (see Figure 9), VCC(5V0) can be switched off using an external PMOS transistor, controlled using one of the GPIO pins of the processor. This helps to reduce the suspend current (ICC(I/O) below 100 A. If the ISP1761 is used in hybrid mode and VCC(5V0) is off during suspend, a 2 ms reset pulse is required when power is switched back to on, before starting to program the resume.
controlled by the CPU 6, 7 VCC(5V0) 3.3 V to 5 V
100 nF
10, 40, 48, 59, 67, 75, 83, 94, 104, 115 85
VCC(I/O)
1.65 V to 3.6 V
100 nF
VREG(1V8) +
10 F
ISP1761
VREG(1V8) 5, 50, 118
100 nF
100 nF
VREG(3V3) 9
10 F
+
100 nF
126
004aaa676
VCC(C_IN)
3.3 V
100 nF
A 4.7 F to 10 F capacitor is required on any one of the pins--5, 50 and 118.
Fig 9. Hybrid mode
Table 7 shows the status of output pins during hybrid mode.
Table 7: Pins DATA[31:0], A[17:1], TEST, HC_IRQ, DC_IRQ, HC_DREQ, DC_DREQ, HC_DACK, DC_DACK, HC_SUSPEND/WAKEUP_N, DC_SUSPEND/WAKEUP_N CS_N, RESET_N, RD_N, WR_N Pin status during hybrid mode VCC(I/O) on on off on off VCC(5V0) on off X X X Status normal high-Z undefined input undefined
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7.8 Overcurrent detection
The ISP1761 can implement a digital or analog overcurrent detection scheme. Bit 15 of the HW Mode Control register can be programmed to select the analog or digital overcurrent detection. An analog overcurrent detection circuit is integrated on-chip. The main features of this circuit are self reporting, automatic resetting, low-trip time and low cost. This circuit offers an easy solution at no extra hardware cost on the board. The port power will be automatically disabled by the ISP1761 on an overcurrent event occurrence, by deasserting the PSWn_N signal without any software intervention. When using the integrated analog overcurrent detection, the range of the overcurrent detection voltage for the ISP1761 is 45 mV to 90 mV. Calculation of the external components should be based on the 45 mV value, with the actual overcurrent detection threshold usually positioned in the middle of the interval. For an overcurrent limit of 500 mA per port, a PMOS transistor with RDSON of approximately 100 m is required. If a PMOS transistor with a lower RDSON is used, the analog overcurrent detection can be adjusted using a series resistor; see Figure 10. VPMOS = VOC(TRIP) = VTRIP(intrinsic) - (IOC(nom) x Rtd), where: VPMOS = voltage drop on PMOS IOC(nom) = 1 A.
5V
IOC Rtd(1) REF5V PSWn_N OCn_N
ISP1761
004aaa662
(1) Rtd is optional.
Fig 10. Adjusting analog overcurrent detection limit (optional)
The digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as: LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These devices are controlled by PSWn_N signals corresponding to each port. In the case of overcurrent occurrence, these devices will assert OCn_N signals. On OCn_N assertion, the ISP1761 cuts off the port power by deasserting PSWn_N. The external integrated power switch will also automatically cut-off the port power in the case of an overcurrent event, by implementing a thermal shutdown. An internal delay filter of 1 ms to 3 ms will prevent false overcurrent reporting because of in-rush currents when plugging a USB device.
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7.9 Power-On Reset (POR)
When VCC(5V0) is directly connected to the RESET_N pin, the internal POR pulse width (tPORP) will be typically 800 ns. The pulse is started when VCC(5V0) rises above VTRIP (1.2 V). To give a better view of the functionality, Figure 11 shows a possible curve of VCC(5V0) with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, < 11 s), the internal POR pulse will not react and will remain LOW. The internal POR starts with a 1 at t0. At t1, the detector will see the passing of the trip level and a delay element will add another tPORP before it drops to 0. The internal POR pulse will be generated whenever VCC(5V0) drops below VTRIP for more than 11 s.
VCC(5V0) VTRIP
t0
t1 tPORP
t2
t3 tPORP
t4
t5 PORP(1)
004aaa584
(1) PORP = Power-On Reset Pulse.
Fig 11. Internal power-on reset timing
The recommended RESET input pulse length at power-on should be at least 2 ms to ensure that internal clocks are stable. The RESET_N pin can be either connected to VCC(I/O) (using the internal POR circuit) or externally controlled (by the microcontroller, ASIC, and so on). Figure 12 shows the availability of the clock with respect to the external POR.
RESET_N EXTERNAL CLOCK
004aaa583
A
Stable external clock is available at A.
Fig 12. Clock with respect to the external power-on reset
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8. Host Controller
Table 8 shows the bit description of the registers.
* All registers range from 0000h to 03FFh. These registers can be read or written as
double word, that is 32-bit data.
* Operational registers range from 0000h to 01FFh. Host Controller-specific and OTG
Controller-specific registers range from 0300h to 03FFh. Peripheral Controller-specific registers range from 0200h to 02FFh.
* 17 address lines (15/14 addresses--necessary for addressing of up to 64 kB range
on a 16-bit/32-bit data bus configuration + additional 2 addresses for bank select/virtual segmentation for memory address access time improvement). A0 is not defined because 8-bit access is not implemented.
Table 8: Address 0000h 0002h 0004h 0008h 0020h 0024h 0028h 002Ch 0030h 0060h 0064h 0130h 0134h 0138h 0140h 0144h 0148h 0150h 0154h 0158h 0300h 0304h 0308h 030Ch 0330h 0334h
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Host Controller-specific register overview Register CAPLENGTH HCIVERSION HCSPARAMS HCCPARAMS USBCMD USBSTS USBINTR FRINDEX CTRLDSSEGMENT CONFIGFLAG PORTSC1 ISO PTD Done Map ISO PTD Skip Map ISO PTD Last PTD INT PTD Done Map INT PTD Skip Map INT PTD Last PTD ATL PTD Done Map ATL PTD Skip Map ATL PTD Last PTD HW Mode Control HcChipID HcScratch SW Reset HcDMAConfiguration HcBufferStatus Reset value 20h 0100h 0000 0011h 0000 0086h 0008 0000h 0000 1000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 2000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h FFFF FFFFh 0000 0000h 0000 0000h 0001 1761h 0000 0000h 0000 0000h 0000 0000h 0000 0000h References Section 8.1.1 on page 32 Section 8.1.2 on page 32 Section 8.1.3 on page 32 Section 8.1.4 on page 33 Section 8.2.1 on page 34 Section 8.2.2 on page 35 Section 8.2.3 on page 36 Section 8.2.4 on page 36 Section 8.2.5 on page 37 Section 8.2.6 on page 37 Section 8.2.7 on page 38 Section 8.2.8 on page 40 Section 8.2.9 on page 40 Section 8.2.10 on page 40 Section 8.2.11 on page 41 Section 8.2.12 on page 41 Section 8.2.13 on page 41 Section 8.2.14 on page 42 Section 8.2.15 on page 42 Section 8.2.16 on page 42 Section 8.3.1 on page 42 Section 8.3.2 on page 44 Section 8.3.3 on page 44 Section 8.3.4 on page 44 Section 8.3.5 on page 45 Section 8.3.6 on page 46
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EHCI capability registers
EHCI operational registers
Configuration registers
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Host Controller-specific register overview...continued Register ATL Done Timeout Memory Edge Interrupt Count DMA Start address Power Down Control HcInterrupt HcInterruptEnable ISO IRQ Mask OR INT IRQ Mask OR ATL IRQ Mask OR ISO IRQ Mask AND INT IRQ Mask AND ATL IRQ Mask AND Reset value 0000 0000h 0000 0000h 0000 000Fh 0000 0000h 03E8 1BA0h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h 0000 0000h References Section 8.3.7 on page 47 Section 8.3.8 on page 47 Section 8.3.9 on page 48 Section 8.3.10 on page 49 Section 8.3.11 on page 50 Section 8.4.1 on page 52 Section 8.4.2 on page 54 Section 8.4.3 on page 56 Section 8.4.4 on page 56 Section 8.4.5 on page 56 Section 8.4.6 on page 56 Section 8.4.7 on page 57 Section 8.4.8 on page 57
Table 8: Address 0338h 033Ch 0340h 0344h 0354h 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch
Interrupt registers
8.1 EHCI capability registers
8.1.1 CAPLENGTH register (R: 0000h)
The bit description of the Capability Length (CAPLENGTH) register is given in Table 9.
Table 9: Bit 7 to 0 CAPLENGTH register: bit description Symbol CAPLENGTH [7:0] Access R Value 20h Description Capability Length: This is used as an offset. It is added to the register base to find the beginning of the operational register space.
8.1.2 HCIVERSION register (R: 0002h)
Table 10 shows the bit description of the Host Controller Interface Version Number (HCIVERSION) register.
Table 10: Bit HCIVERSION register: bit description Access Value R 0100h Description Host Controller Interface Version Number: It contains a BCD encoding of the version number of the interface to which the Host Controller interface conforms.
Symbol
15 to 0 HCIVERSION[15:0]
8.1.3 HCSPARAMS register (R: 0004h)
The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 11.
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Table 11: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
HCSPARAMS register: bit allocation 31 0 R 23 30 0 R 22 DPN[3:0] 0 R 15 0 R 7 PRR 0 R 0 R Table 12: Bit 31 to 24 23 to 20 19 to 17 16 15 to 12 0 R 14 N_CC[3:0] 0 R 6 reserved 0 R 0 R 5 0 R 4 PPC 1 R 0 R 0 R 3 0 R 2 0 R 0 R 13 0 R 12 0 R 11 29 0 R 21 28 reserved 0 R 20 0 R 19 0 R 18 reserved 0 R 10 N_PCC[3:0] 0 R 1 0 R 0 R 0 1 R 0 R 9 0 R 17 0 R 16 P_INDI CATOR 0 R 8 27 26 25 24
N_PORTS[3:0]
HCSPARAMS register: bit description Symbol DPN[3:0] P_INDICATOR N_CC[3:0] Description [1] reserved; write logic 0 Debug Port Number: This field identifies which of the Host Controller ports is the debug port. reserved; write logic 0 Port Indicators: This bit indicates whether the ports support port indicator control. Number of Companion Controller: This field indicates the number of companion controllers associated with this Hi-Speed USB Host Controller. Number of Ports per Companion Controller: This field indicates the number of ports supported per companion Host Controller. Port Routing Rules: This field indicates the method used for mapping ports to the companion controllers. reserved; write logic 0 Port Power Control: This field indicates whether the Host Controller implementation includes port power control. N_Ports: This field specifies the number of physical downstream ports implemented on this Host Controller.
11 to 8 7 6 to 5 4 3 to 0
[1]
N_PCC[3:0] PRR PPC N_PORTS[3:0]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.1.4 HCCPARAMS register (R: 0008h)
The Host Controller Capability Parameters (HCCPARAMS) register is a 4 B register, and the bit allocation is given in Table 13.
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Table 13: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
HCCPARAMS register: bit allocation 31 0 R 23 0 R 15 0 R 7 1 R 30 0 R 22 0 R 14 0 R 6 IST[3:0] 0 R Table 14: Bit 15 to 8 7 to 4 31 to 16 EECP[7:0] IST[3:0] 0 R 0 R 29 0 R 21 0 R 13 0 R 5 28 reserved 0 R 20 reserved 0 R 12 EECP[7:0] 0 R 4 0 R 3 reserved 0 R 0 R 2 ASPC 1 R 0 R 1 PFLF 1 R 0 R 0 64AC 0 R 0 R 11 0 R 10 0 R 9 0 R 8 0 R 19 0 R 18 0 R 17 0 R 16 27 26 25 24
HCCPARAMS register: bit description Symbol Description [1] reserved; write logic 0 EHCI Extended Capabilities Pointer: Default = implementation dependent. This optional field indicates the existence of a capabilities list. Isochronous Scheduling Threshold: Default = implementation dependent. This field indicates, relative to the current position of the executing Host Controller, where software can reliably update the isochronous schedule. reserved; write logic 0 Asynchronous Scheduling Park Capability: Default = implementation dependent. If this bit is set to logic 1, the Host Controller supports the park feature for high-speed queue heads in the Asynchronous Schedule. Programmable Frame List Flag: Default = implementation dependent. If this bit is cleared, the system software must use a frame list length of 1024 elements with this Host Controller. If PFLF is set, the system software can specify and use a smaller frame list and configure the host through the USBCMD register FLS field.
3 2
ASPC
1
PFLF
0
[1]
64AC
64-bit addressing capability: This field documents the addressing range capability.
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2 EHCI operational registers
8.2.1 USBCMD register (R/W: 0020h)
The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller. Writing to this register causes a command to be executed. Table 15 shows the USBCMD register bit allocation.
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Table 15: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
USBCMD register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 LHCR 0 R/W 0 R/W 0 R/W 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 29 0 R/W 21 0 R/W 13 0 R/W 5 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 RS 0 R/W 1 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 16: Bit 31 to 8 7
USBCMD register: bit description Symbol LHCR Description [1] reserved Light Host Controller Reset (optional): If implemented, it allows the driver software to reset the EHCI controller without affecting the state of the ports or the relationship to the companion Host Controllers. If not implemented, a read of this field will always return logic 0. reserved Run/Stop: 1 = Run, 0 = Stop. When set, the Host Controller executes the schedule.
6 to 1 0
[1]
RS
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.2 USBSTS register (R/W: 0024h)
The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register. Software clears the register bits by writing ones to them. The bit allocation is given in Table 17.
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Table 17: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
USBSTS register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 reserved [1] 0 R/W 0 R/W 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 1 R/W 4 0 R/W 3 FLR 0 R/W 0 R/W 2 PCD 0 R/W 0 R/W 0 R/W 1 reserved [1] 0 R/W 0 R/W 0 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 18: Bit 31 to 4 3 2
USBSTS register: bit description Symbol Description [1] FLR PCD reserved; write logic 0 Frame List Rollover: The Host Controller sets this bit to logic 1 when the Frame List Index rolls over from its maximum value to zero. Port Change Detect: The Host Controller sets this bit to logic 1 when any port, where the PO bit is cleared, has a change to a one or a FPR bit changes to a one as a result of a J-K transition detected on a suspended port. reserved
1 to 0
[1]
-
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.3 USBINTR register (R/W: 0028h)
All the bits in this register are reserved.
8.2.4 FRINDEX register (R/W: 002Ch)
The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic frame list. The register updates every 125 s (once each microframe). Bits n to 3 are used to select a particular entry in the Periodic Frame List during periodic schedule execution. The number of bits used for the index depends on the size of the frame list as set by the system software in the FLS (Frame List Size) field of the USBCMD register. This register must be written as a Double Word. A Word-only write (16-bit mode) produces undefined results. This register cannot be written unless the Host Controller is in the halted state as indicated by the HCH (HCHalted) bit. A write to this register while the RS (Run/Stop) bit is set produces undefined results. Writes to this register also affect the SOF value. The bit allocation is given in Table 19.
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Table 19: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
FRINDEX register: bit allocation 31 0 R/W 23 0 R/W 15 reserved [1] 0 R/W 7 0 R/W 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 0 R/W 30 0 R/W 22 0 R/W 14 29 0 R/W 21 0 R/W 13 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 11 0 R/W 3 0 R/W 0 R/W 10 0 R/W 2 0 R/W 0 R/W 9 0 R/W 1 0 R/W 0 R/W 8 0 R/W 0 0 R/W 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
FRINDEX[13:8]
FRINDEX[7:0]
The reserved bits should always be written with the reset value.
Table 20: Bit 13 to 0 31 to 14 -
FRINDEX register: bit description Symbol Description [1] reserved
FRINDEX[13:0] Frame Index: Bits in this register are used for the frame number in the SOF packet and as the index into the Frame List. The value in this register increments at the end of each time frame (for example, microframe).
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.5 CTRLDSSEGMENT register (R/W: 0030h)
The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the most significant address bits (bits 63 to 32) for all EHCI data structures. If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is cleared, then this register is not used and software cannot write to it (reading from this register returns zero). If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is set, this register is used with link pointers to construct 64-bit addresses to EHCI control data structures. This register is concatenated with the link pointer from either the PERIODICLISTBASE, ASYNCLISTADDR, or any control data structure link field to construct a 64-bit address. This register allows the host software to locate all control data structures within the same 4 GB memory segment.
8.2.6 CONFIGFLAG register (R/W: 0060h)
The bit allocation of the Configure Flag (CONFIGFLAG) register is given in Table 21.
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Table 21: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
CONFIGFLAG register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W 29 0 R/W 21 0 R/W 13 0 R/W 5 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 CF 0 R/W 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 22: Bit 0 31 to 1 -
CONFIGFLAG register: bit description reserved Configure Flag: The host software sets this bit as the last action when it is configuring the Host Controller. This bit controls the default port-routing control logic.
Symbol Description [1] CF
[1]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0.
8.2.7 PORTSC1 register (R, R/W, R/WC (field dependent): 0064h)
The Port Status and Control (PORTSC) register (bit allocation: Table 23) is in the power well. It is reset by hardware only when the auxiliary power is initially applied or in response to a Host Controller reset. The initial conditions of a port are:
* No peripheral connected * Port disabled.
If the port has power control, software cannot change the state of the port until it sets the port power bits. Software must not attempt to change the state of the port until the power is stable on the port (maximum delay is 20 ms from the transition).
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Table 23: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
PORTSC 1 register: bit allocation 31 0 R/W 23 0 R/W 15 PIC[1:0] 0 R 7 SUSP 0 R/W 0 R 6 FPR 0 R/W 0 R/W 30 0 R/W 22 reserved [1] 0 R/W 14 0 R/W 13 PO 1 R/W 5 0 R/W 12 PP 0 R/W 4 reserved [1] 0 R/W 0 R/W 0 R/W 3 0 R/W 11 LS[1:0] 0 R/W 2 PED 0 R/W 0 R/W 10 29 0 R/W 21 28 reserved [1] 0 R/W 20 0 R/W 19 0 R/W 18 PTC[3:0] 0 R/W 9 reserved [1] 0 R/W 1 ECSC 0 R/W 0 R/W 8 PR 0 R 0 ECCS 0 R 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 24: Bit 31 to 20 19 to 16
PORTSC 1 register: bit description Symbol PTC[3:0] Description [1] reserved Port Test Control: When this field is zero, the port is not operating in a test mode. A non-zero value indicates that it is operating in test mode indicated by the value. Port Indicator Control: Writing to this field has no effect if the P_INDICATOR bit in the HCSPARAMS register is logic 0. For a description on how these bits are implemented, refer to Universal Serial Bus Specification Rev. 2.0. [2]
15 to 14
PIC[1:0]
13
PO
Port Owner: This bit unconditionally goes to logic 0 when the configured bit in the CONFIGFLAG register makes a logic 0 to logic 1 transition. This bit unconditionally goes to logic 1 whenever the configured bit is logic 0. Port Power: The function of this bit depends on the value of the PPC (Port Power Control) field in the HCSPARAMS register. Line Status: This field reflect the current logical levels of the DP (bit 11) and DM (bit 10) signal lines. reserved Port Reset: Logic 1 means the port is in the reset state. Logic 0 means the port is not in reset. [2] Suspend: Logic 1 means the port is in the suspend state. Logic 0 means the port is not suspended. [2] Force Port Resume: Logic 1 means resume detected or driven on the port. Logic 0 means no resume (K-state) detected or driven on the port. [2] reserved
12 11 to 10 9 8 7 6
PP LS[1:0] PR SUSP FPR
5 to 3
-
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PORTSC 1 register: bit description...continued Symbol PED ECSC ECCS Description [1] Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable. [2] Connect Status Change: Logic 1 means change in ECCS. Logic 0 means no change. [2] Current Connect Status: Logic 1 indicates a peripheral is present on the port. Logic 0 indicates no peripheral is present. [2]
Table 24: Bit 2 1 0
[1] [2]
For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0. These fields read logic 0, if the PP (Port Power) bit in register PORTSC 1 is logic 0.
8.2.8 ISO PTD Done Map register (R: 0130h)
The bit description of the register is given in Table 25.
Table 25: Bit 31 to 0 ISO PTD Done Map register: bit description Symbol Access Value 0000 0000h Description ISO PTD Done Map: Done map for each of the 32 PTDs for the ISO transfer ISO_PTD_DONE R _MAP[31:0]
This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of new executed PTDs.
8.2.9 ISO PTD Skip Map register (R/W: 0134h)
Table 26 shows the bit description of the register.
Table 26: Bit 31 to 0 ISO PTD Skip Map register: bit description Symbol ISO_PTD_SKIP_ MAP[31:0] Access Value R/W FFFF FFFFh Description ISO PTD Skip Map: Skip map for each of the 32 PTDs for the ISO transfer
When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer.
8.2.10 ISO PTD Last PTD register (R/W: 0138h)
Table 27 shows the bit description of the ISO PTD Last PTD register.
Table 27: Bit 31 to 0 ISO PTD Last PTD register: bit description Symbol ISO_PTD_ LAST_ PTD[31:0] Access Value R/W 0000 0000h Description ISO PTD last PTD: Last PTD of the 32 PTDs. 1h -- One PTD in ISO 2h -- Two PTDs in ISO 4h -- Three PTDs in ISO.
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Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = 1) in that PTD category. Subsequently, the process will restart with the first PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective memory space) would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD.
8.2.11 INT PTD Done Map register (R: 0140h)
The bit description of the register is given in Table 28.
Table 28: Bit 31 to 0 INT PTD Done Map register: bit description Symbol Access Value 0000 0000h Description INT PTD Done Map: Done map for each of the 32 PTDs for the INT transfer INT_PTD_DONE_ R MAP[31:0]
This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of new executed PTDs.
8.2.12 INT PTD Skip Map register (R/W: 0144h)
Table 29 shows the bit description of the INT PTD Skip Map register.
Table 29: Bit 31 to 0 INT PTD Skip Map register: bit description Symbol Access Value FFFF FFFFh Description INT PTD Skip Map: Skip map for each of the 32 PTDs for the INT transfer INT_PTD_SKIP R/W _MAP[31:0]
When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer.
8.2.13 INT PTD Last PTD register (R/W: 0148h)
The bit description of the register is given in Table 30.
Table 30: Bit 31 to 0 INT PTD Last PTD register: bit description Symbol INT_PTD_ LAST_ PTD[31:0] Access R/W Value 0000 0000h Description INT PTD Last PTD: Last PTD of the 32 PTDs. 1h -- One PTD in INT 2h -- Two PTDs in INT 3h -- Three PTDs in INT.
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = 1) in that PTD category. Subsequently, the process will restart with the first PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective memory space) would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD.
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8.2.14 ATL PTD Done Map register (R: 0150h)
Table 31 shows the bit description of the ATL PTD Done Map register.
Table 31: Bit 31 to 0 ATL PTD Done Map register: bit description Symbol ATL_PTD_DONE_ MAP[31:0] Access R Value 0000 0000h Description ATL PTD Done Map: Done map for each of the 32 PTDs for the ATL transfer
This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will reflect the updated status of new executed PTDs.
8.2.15 ATL PTD Skip Map register (R/W: 0154h)
The bit description of the register is given in Table 32.
Table 32: Bit 31 to 0 ATL PTD Skip Map register: bit description Symbol ATL_PTD_SKIP_ MAP[31:0] Access R/W Value Description FFFF FFFFh ATL PTD Skip Map: Skip map for each of the 32 PTDs for the ATL transfer
When a bit in the PTD Skip map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer.
8.2.16 ATL PTD Last PTD register (R/W: 0158h)
The bit description of the ATL PTD Last PTD register is given in Table 33.
Table 33: Bit ATL PTD Last PTD register: bit description Symbol Access Value R/W 0000 0000h Description ATL PTD Last PTD: Last PTD of the 32 PTDs. 1h -- One PTD in ATL 2h -- Two PTDs in ATL 4h -- Three PTDs in ATL.
31 to 0 ATL_PTD_ LAST_ PTD[31:0]
Once the LastPTD bit corresponding to a PTD is set, this will be the last PTD processed (checking V = 1) in that PTD category. Subsequently, the process will restart with the first PTD (of that group). This is useful to reduce the time in which all the PTDs (the respective memory space) would be checked, especially if only a few PTDs are defined. The LastPTD bit must be normally set to a higher position than any other position indicated by the NextPTDPointer from an active PTD.
8.3 Configuration registers
8.3.1 HW Mode Control register (R/W: 0300h)
Table 34 shows the bit allocation of the register.
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Table 34: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
HW Mode Control register: bit allocation 31 ALL_ATX_ RESET 0 R/W 23 0 R/W 15 ANA_DIGI _OC 0 R/W 7 reserved 0 R/W 0 R/W 6 DACK_ POL 0 R/W 0 R/W 22 0 R/W 14 0 R/W 21 0 R/W 13 reserved [1] 0 R/W 5 DREQ_ POL 0 R/W 0 R/W 0 R/W 4 reserved [1] 0 R/W 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 11 DEV_ DMA 0 R/W 3 0 R/W 10 COMN_ IRQ 0 R/W 2 INTR_POL 0 R/W 0 R/W 9 COMN_ DMA 0 R/W 1 INTR_ LEVEL 0 R/W 0 R/W 8 DATA_BUS _WIDTH 1 R/W 0 GLOBAL_ INTR_EN 0 R/W 30 29 28 27 reserved [1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 26 25 24
The reserved bits should always be written with the reset value.
Table 35: Bit 31
HW Mode Control register: bit description Symbol ALL_ATX_ RESET Description All ATX Reset: For debugging purposes (not used normally). 1 -- Enable reset, then write back logic 0 0 -- No reset. reserved; write logic 0 Analog Digital Overcurrent: This bit selects analog or digital overcurrent detection on pins OC1_N/VBUS, OC2_N and OC3_N. 0 -- Digital overcurrent 1 -- Analog overcurrent.
30 to 16 15 ANA_DIGI_OC
14 to 12 11 DEV_DMA
reserved; write logic 0 Device DMA: When this bit and bit 9 are set, DC_DREQ and DC_DACK peripheral signals are selected on the HC_DREQ and HC_DACK pins Common IRQ: When this bit is set, DC_IRQ will be generated on the HC_IRQ pin. Common DMA: When this bit and bit 11 are set, the DC_DREQ and DC_DACK peripheral signals are routed to the HC_DREQ and HC_DACK pins. Data Bus Width: 0 -- defines a 16-bit data bus width 1 -- sets a 32-bit data bus width. Remark: Setting this bit will affect all the controllers on the chip (Host Controller, Peripheral Controller and OTG Controller).
10 9
COMN_INT COMN_DMA
8
DATA_BUS_ WIDTH
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HW Mode Control register: bit description...continued Symbol DACK_POL Description reserved; write logic 0 DACK Polarity: 1 -- indicates that the DACK input is active HIGH 0 -- indicates active LOW.
Table 35: Bit 7 6
5
DREQ_POL
DREQ Polarity: 1 -- indicates that the DREQ output is active HIGH 0 -- indicates active LOW.
4 to 3 2
INTR_POL
reserved; write logic 0 Interrupt Polarity: 0 -- active LOW 1 -- active HIGH.
1
INTR_LEVEL
Interrupt Level: 0 -- INT level triggered 1 -- INT is edge triggered. A pulse of certain width is generated.
0
GLOBAL_INTR Global Interrupt Enable: This bit must be set to logic 1 to enable IRQ _EN signal assertion. 0 -- IRQ assertion disabled. IRQ will never be asserted, regardless of other settings or IRQ events 1 -- IRQ assertion enabled. IRQ will be asserted according to the HcInterruptEnable register, and events setting and occurrence
8.3.2 HcChipID register (R: 0304h)
Read this register to get the ID of the ISP1761. This upper word of the register contains the hardware version number and the lower word contains the chip ID. Table 36 shows the bit description of the register.
Table 36: Bit 31 to 0 HcChipID register: bit description Symbol CHIPID [31:0] Access Value R 0001 1761h Description Chip ID: This register represents the hardware version number (0001h) and the chip ID (1761h) for the Host Controller.
8.3.3 HcScratch register (R/W: 0308h)
This register is for testing and debugging purposes only. The value read back must be the same as the value that was written. The bit description of this register is given in Table 37.
Table 37: Bit 31 to 0 HcScratch register: bit description Symbol Access Value 0000 0000h Description Scratch: For testing and debugging purposes SCRATCH[31:0] R/W
8.3.4 SW Reset register (R/W: 030Ch)
Table 38 shows the bit allocation of the register.
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Table 38: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
SW Reset register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 30 0 R/W 22 0 R/W 14 0 R/W 6 29 0 R/W 21 0 R/W 13 0 R/W 5 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 reserved [1] 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 RESET_ HC 0 R/W 0 R/W 0 RESET_ ALL 0 R/W 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
Table 39: Bit 31 to 2 1
SW Reset register: bit description Symbol RESET_HC Description reserved; write logic 0 Reset Host Controller: Reset only the Host Controller-specific registers (only registers with address below 300h). 0 -- No reset 1 -- Enable reset.
0
RESET_ALL
Reset All: Reset all the Host Controller and CPU interface registers. 0 -- No reset 1 -- Enable reset.
8.3.5 HcDMAConfiguration register (R/W: 0330h)
The bit allocation of the HcDMAConfiguration register is given in Table 40.
Table 40: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 HcDMAConfiguration register: bit allocation 31 30 29 28 0 R/W 20 0 R/W 27 0 R/W 19 0 R/W 26 0 R/W 18 0 R/W 25 0 R/W 17 0 R/W 24 0 R/W 16 0 R/W DMA_COUNTER[23:16]
DMA_COUNTER[15:8]
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13 0 R/W 5 reserved [1] 12 0 R/W 4 11 0 R/W 3 10 0 R/W 2 9 0 R/W 1 ENABLE_ DMA 0 R/W 8 0 R/W 0 DMA_READ _WRITE_ SEL 0 R/W
Bit Symbol Reset Access Bit Symbol
15 0 R/W 7
14 0 R/W 6
DMA_COUNTER[7:0]
BURST_LEN[1:0]
Reset Access
[1]
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
The reserved bits should always be written with the reset value.
Table 41: Bit 31 to 8
HcDMAConfiguration register: bit description Symbol DMA_ COUNTER [23:0] BURST_LEN [1:0] Description DMA Counter: The number of bytes to be transferred (read or write). Remark: Different number of bursts will be generated for the same transfer length programmed in 16-bit and 32-bit modes because DMA_COUNTER is in number of bytes. reserved DMA Burst Length: 00 -- Single DMA burst 01 -- 4-cycle DMA burst 10 -- 8-cycle DMA burst 11 -- 16-cycle DMA burst.
7 to 4 3 to 2
1
ENABLE_DMA
Enable DMA: 0 -- Terminate DMA 1 -- Enable DMA.
0
DMA_READ_ WRITE_SEL
DMA Read or Write Select: Indicates if the DMA operation is a write or read (to or from the ISP1761). 0 -- DMA write to the ISP1761 internal RAM is set 1 -- DMA read from the ISP1761 internal RAM.
8.3.6 HcBufferStatus register (R/W: 0334h)
Table 42 shows the bit allocation of the HcBufferStatus register.
Table 42: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W HcBufferStatus register: bit allocation 31 30 29 28 reserved [1] 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
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13 0 R/W 5 reserved [1] 12 reserved [1] 0 R/W 4 11 0 R/W 3 10 0 R/W 2 ISO_BUF_ FILL 0 R/W 0 R/W 0 R/W 9 0 R/W 1 INT_BUF_ FILL 0 R/W 8 0 R/W 0 ATL_BUF_ FILL 0 R/W
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 0 R/W 7
14 0 R/W 6
0 R/W
0 R/W
0 R/W
The reserved bits should always be written with the reset value.
Table 43: Bit 31 to 3 2
HcBufferStatus register: bit description Symbol ISO_BUF_ FILL Description reserved ISO Buffer Filled: 1 -- Indicates one of the ISO PTDs is filled, and the ISO PTD area will be processed 0 -- Indicates there is no PTD in this area. Therefore, processing of the ISO PTDs will be completely skipped.
1
INT_BUF_ FILL
INT Buffer Filled: 1 -- Indicates one of the INT PTDs is filled, and the INT PTD area will be processed 0 -- Indicates there is no PTD in this area. Therefore, processing of the INT PTDs will be completely skipped.
0
ATL_BUF_ FILL
ATL Buffer Filled: 1 -- Indicates one of the ATL PTDs is filled, and the ATL PTD area will be processed 0 -- Indicates there is no PTD in this area. Therefore, processing of the ATL PTDs will be completely skipped.
8.3.7 ATL Done Timeout register (R/W: 0338h)
The bit description of the ATL Done Timeout register is given in Table 44.
Table 44: Bit ATL Done Timeout register: bit description Access Value Description 0000 0000h ATL Done Timeout: This register determines the ATL done timeout interrupt. This register defines the timeout in ms after which the ISP1761 asserts the INT line, if enabled. It is applicable to the ATL done PTDs only.
Symbol
31 to 0 ATL_DONE_ R/W TIMEOUT [31:0]
8.3.8 Memory register (R/W: 033Ch)
The Memory register contains the base memory read address and the respective bank. This register needs to be set only before a first memory read cycle. Once written, the address will be latched for the bank and will be incremented for every read of that bank until a new address for that bank is written to change the address pointer. The bit description of the register is given in Table 45.
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Table 45: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Memory register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 7 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 6 0 R/W 29 0 R/W 21 reserved [1] 0 R/W 13 0 R/W 5 0 R/W 0 R/W 12 0 R/W 4 0 R/W 0 R/W 11 0 R/W 3 0 R/W 0 R/W 10 0 R/W 2 0 R/W 28 reserved [1] 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W 27 26 25 24
MEM_BANK_SEL[1:0]
START_ADDR_MEM_READ[15:8]
START_ADDR_MEM_READ[7:0]
The reserved bits should always be written with the reset value.
Table 46: Bit 31 to 18 -
Memory register: bit description Symbol Description reserved Memory Bank Select: Up to four memory banks can be selected. For details on internal memory read description, see Section 7.3.1. Applicable to PIO mode memory read or write data transfers only.
17 to 16 MEM_BANK_ SEL[1:0] 15 to 0
START_ Start Address for Memory Read Cycles: The start address for a ADDR_MEM_ series of memory read cycles at incremental addresses in a contiguous READ[15:0] space. Applicable to PIO mode memory read data transfers only.
8.3.9 Edge Interrupt Count register (R/W: 0340h)
Table 47 shows the bit allocation of the register.
Table 47: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 23 0 R/W 22 0 R/W 21 Edge Interrupt Count register: bit allocation 31 30 29 28 0 R/W 20 reserved [1] 0 R/W 0 R/W 0 R/W 0 R/W 27 0 R/W 19 26 0 R/W 18 25 0 R/W 17 24 0 R/W 16 MIN_WIDTH[7:0]
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13 0 R/W 5 0 R/W 12 0 R/W 4 0 R/W 11 0 R/W 3 1 R/W 10 0 R/W 2 1 R/W 9 0 R/W 1 1 R/W 8 0 R/W 0 1 R/W
Bit Symbol Reset Access Bit Symbol Reset Access
[1]
15 0 R/W 7 0 R/W
14 0 R/W 6 0 R/W
NO_OF_CLK[15:8]
NO_OF_CLK[7:0]
The reserved bits should always be written with the reset value.
Table 48: Bit 31 to 24
Edge Interrupt Count register: bit description Symbol MIN_ WIDTH[7:0] Description Minimum Width: Indicates the minimum width between two edge interrupts in SOFs (1 SOF = 125 s). This is not valid for level interrupts. A count of zero means that interrupts occur as and when an event occurs. reserved Number of Clocks: Count in number of clocks that the edge interrupt must be kept asserted on the interface.16 clocks of 60 MHz on POR if this register has a value of 0000h. The default IRQ pulse width is approximately 500 ns.
23 to 16 15 to 0
NO_OF_ CLK[15:0]
8.3.10 DMA Start Address register (W: 0344h)
This register defines the start address select for the DMA read and write operations. See Table 49 for bit allocation.
Table 49: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
DMA Start Address register: bit allocation 31 0 W 23 0 W 15 0 W 7 0 W 30 0 W 22 0 W 14 0 W 6 0 W 29 0 W 21 0 W 13 0 W 5 0 W 28 reserved [1] 0 W 20 reserved [1] 0 W 12 0 W 4 0 W 0 W 11 0 W 3 0 W 0 W 10 0 W 2 0 W 0 W 9 0 W 1 0 W 0 W 8 0 W 0 0 W 0 W 19 0 W 18 0 W 17 0 W 16 27 26 25 24
START_ADDR_DMA[15:8]
START_ADDR_DMA[7:0]
The reserved bits should always be written with the reset value.
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DMA Start Address register: bit description Symbol START_ADDR _DMA[15:0] Description reserved Start Address for DMA: The start address for DMA read or write cycles.
Table 50: Bit 31 to 16 15 to 0
8.3.11 Power Down Control register (R/W: 0354h)
This register is used to turn off power to the internal blocks of the ISP1761 to obtain maximum power savings. Table 51 shows the bit allocation of the register.
Table 51: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
Power Down Control register: bit allocation 31 0 R/W 23 1 R/W 15 30 0 R/W 22 1 R/W 14 reserved [1] 0 R/W 7 reserved [1] 1 R/W 0 R/W 0 R/W 6 0 R/W 5 BIASEN 1 R/W 29 0 R/W 21 1 R/W 13 28 0 R/W 20 0 R/W 12 PORT3_ PD 1 R/W 4 VREG_ON 0 R/W 27 0 R/W 19 1 R/W 11 PORT2_ PD 1 R/W 3 OC3_PWR 0 R/W 26 0 R/W 18 0 R/W 10 VBATDET_ PWR 0 R/W 2 OC2_PWR 0 R/W 1 R/W 1 OC1_PWR 0 R/W 25 1 R/W 17 0 R/W 9 reserved [1] 1 R/W 0 HC_CLK_ EN 0 R/W 24 1 R/W 16 0 R/W 8 CLK_OFF_COUNTER[15:8]
CLK_OFF_COUNTER[7:0]
The reserved bits should always be written with the reset value.
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Power Down Control register: bit description Symbol CLK_OFF_ COUNTER [15:0] Description Clock Off Counter: Determines the wake-up status duration after any wake-up event before the ISP1761 goes back into suspend mode. This timeout is applicable only if, during the given interval, the Host Controller is not programmed back to normal functionality. 03E8h -- The default value. It determines the default wake-up interval of 10 ms. A value of zero implies that the Host Controller never wakes up on any of the events. This may be useful when using the ISP1761 as a peripheral to save power by permanently programming the Host Controller in suspend. FFFFh -- The maximum value. It determines a maximum wake-up time of 500 ms. The setting of this register is based on the 100 kHz 40 % LazyClock frequency. It is a multiple of 10 s period. In 16-bit mode, a write operation to these bits with any value will determine a fixed wake-up time of 50 ms.
Table 52: Bit [1] 31 to 16
15 to 13 12
PORT3_ PD
reserved Port 3 Pull-Down: Controls port 3 pull-down resistors. 0 -- Port 3 pull-down resistors are connected in suspend 1 -- Port 3 pull-down resistors are not connected in suspend. Port 2 Pull-Down: Controls port 2 pull-down resistors. 0 -- Port 2 internal pull-down resistors are connected in suspend 1 -- Port 2 internal pull-down resistors are not connected in suspend. VBAT Detector Powered: Controls the power to the VBAT detector. 0 -- VBAT detector is powered or enabled in suspend 1 -- VBAT detector is not powered or disabled in suspend. reserved; write logic 0 BIAS Circuits Powered: Controls the power to internal BIAS circuits. 0 -- Internal BIAS circuits are not powered in suspend 1 -- Internal BIAS circuits are powered in suspend.
11
PORT2_ PD
10
VBATDET_ PWR
9 to 6 5
BIASEN
4
VREG_ON
VREG Powered: Enables or disables the internal 3.3 V and 1.8 V regulators when the ISP1761 is in suspend. 0 -- Internal regulators are powered in suspend 1 -- Internal regulators are not powered in suspend.
3
OC3_PWR
OC3_N Powered: Controls the powering of the overcurrent detection circuitry for port 3. 0 -- Overcurrent detection is powered on or enabled during suspend 1 -- Overcurrent detection is powered off or disabled during suspend. This may be useful when connecting a faulty device while the system is in standby.
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Power Down Control register: bit description...continued Symbol OC2_PWR Description OC2_N Powered: Controls the powering of the overcurrent detection circuitry for port 2. 0 -- Overcurrent detection is powered on or enabled during suspend 1 -- Overcurrent detection is powered off or disabled during suspend. This may be useful when connecting a faulty device while the system is in standby.
Table 52: Bit [1] 2
1
OC1_PWR
OC1_N Powered: Controls the powering of the overcurrent detection circuitry for port 1. 0 -- Overcurrent detection is powered on or enabled during suspend 1 -- Overcurrent detection is powered off or disabled during suspend. This may be useful when connecting a faulty device while the system is in standby.
0
HC_CLK_ EN
Host Controller Clock Enabled: Controls internal clocks during suspend. 0 -- Clocks are disabled during suspend. This is the default value. Only the LazyClock of 100 kHz 40 % will be left running in suspend if this bit is logic 0. If clocks are stopped during suspend, CLKREADY IRQ will be generated when all clocks are running stable. 1 -- All clocks are enabled even in suspend.
[1]
For a 32-bit operation, the default wake-up counter value is 10 s. For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization.
8.4 Interrupt registers
8.4.1 HcInterrupt register (R/W: 0310h)
The bits of this register indicate the interrupt source, defining the events that determined the INT generation. Clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. All bits must be reset before enabling new interrupt events. These bits will be set, regardless of the setting of bit GLOBAL_INTR_EN in the HW Mode Control register. Table 53 shows the bit allocation of the HcInterrupt register.
Table 53: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
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HcInterrupt register: bit allocation 31 0 R/W 23 0 R/W 15 0 R/W 30 0 R/W 22 0 R/W 14 0 R/W 29 0 R/W 21 0 R/W 13 reserved [1] 0 R/W 0 R/W 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 11 0 R/W 10 OTG_IRQ 0 R/W 0 R/W 9 ISO_IRQ 0 R/W 0 R/W 8 ATL_IRQ 0 R/W 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
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5 HCSUSP 0 R/W 4 reserved [1] 0 R/W 3 DMA EOTINT 0 R/W 0 R/W 2 reserved [1] 0 R/W 1 0 SOFITLINT 0 R/W
Bit Symbol Reset Access
[1]
7 INT_IRQ 0 R/W
6 CLK READY 0 R/W
The reserved bits should always be written with the reset value.
Table 54: Bit 31 to 11 10 -
HcInterrupt register: bit description Symbol OTG_IRQ Description reserved; write logic 0 OTG_IRQ: Indicates that IRQ was asserted because of events present in the OTG Interrupt Latch register. 0 -- No IRQ was asserted 1 -- IRQ was asserted. For details, see Section 7.4.
9
ISO_IRQ
ISO IRQ: Indicates that IRQ was asserted because an ISO PTD was completed, or the PTDs corresponding to the bits set in the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination were completed. 0 -- No IRQ assertion determined by the completion of ISO PTDs 1 -- IRQ asserted because of completing ISO PTDs. For details, see Section 7.4.
8
ATL_IRQ
ATL IRQ: Indicates that an IRQ was asserted because an ATL PTD was completed, or the PTDs corresponding to the bits set in the ATL IRQ Mask AND or ATL IRQ Mask OR register bits combination were completed. 0 -- No IRQ assertion determined by the completion of ATL PTDs 1 -- IRQ asserted because of completing ATL PTD. For details, see Section 7.4.
7
INT_IRQ
INT IRQ: Indicates that an IRQ was asserted because an INT PTD was completed, or the PTDs corresponding to the bits set in the INT IRQ Mask AND or INT IRQ Mask OR register bits combination were completed. 0 -- No IRQ assertion determined by the completion of INT PTDs 1 -- IRQ asserted because of completing INT PTD. For details, see Section 7.4.
6
CLKREADY
Clock Ready: Indicates that IRQ was asserted as the internal clock signals are running stable. Useful after a power-on or wake-up cycle. 0 -- No CLKREADY event has occurred 1 -- IRQ generated because of a CLKREADY event.
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HcInterrupt register: bit description...continued Symbol HCSUSP Description Host Controller Suspend: Indicates that the Host Controller has entered suspend mode. 0 -- No IRQ generated because of the Host Controller entering suspend mode 1 -- IRQ generated because of the Host Controller entering suspend mode If the Interrupt Service Routine (ISR) accesses the ISP1761, it will wake up for the time specified in bits 31 to 16 of the Power Down Control register.
Table 54: Bit 5
4 3
DMAEOT INT
reserved; write logic 0 DMA EOT Interrupt: Indicates DMA transfer completion. 0 -- DMA transfer is not complete 1 -- IRQ asserted because the DMA transfer is complete. reserved; write logic 0 SOT ITL Interrupt: 0 -- No SOF event has occurred 1 -- An SOF event has occurred.
2 to 1 0
SOFITLINT
8.4.2 HcInterruptEnable register (R/W: 0314h)
This register allows enabling or disabling of the IRQ generation because of various events as described in Table 55.
Table 55: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
HcInterruptEnable register: bit allocation 31 0 R/W 23 0 R/W 15 30 0 R/W 22 0 R/W 14 29 0 R/W 21 0 R/W 13 reserved [1] 0 R/W 7 INT_IRQ_E 0 R/W 0 R/W 6 CLK READY _E 0 R/W 0 R/W 5 HCSUSP_ E 0 R/W 0 R/W 4 reserved [1] 0 R/W 0 R/W 3 DMAEOT INT _E 0 R/W 0 R/W 28 reserved [1] 0 R/W 20 reserved [1] 0 R/W 12 0 R/W 11 0 R/W 10 OTG_IRQ_ E 0 R/W 2 reserved [1] 0 R/W 0 R/W 9 ISO_IRQ_ E 0 R/W 1 0 R/W 8 ATL_IRQ _E 0 R/W 0 SOFITLINT _E 0 R/W 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 27 26 25 24
The reserved bits should always be written with the reset value.
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HcInterruptEnable register: bit description Symbol OTG_IRQ_E Description reserved; write logic 0 OTG_IRQ Enable: Controls the IRQ assertion because of events present in the OTG Interrupt Latch register. 0 -- No IRQ will be asserted 1 -- IRQ will be asserted. For details, see Section 7.4.
Table 56: Bit 31 to 11 10
9
ISO_IRQ_E
ISO IRQ Enable: Controls the IRQ assertion because of completing one or more ISO PTDs matching the ISO IRQ Mask AND or ISO IRQ Mask OR register bits combination. 0 -- No IRQ will be asserted because of completing ISO PTDs 1 -- IRQ will be asserted. For details, see Section 7.4.
8
ATL_IRQ_E
ATL IRQ Enable: Controls the IRQ assertion because of completing one or more ATL PTDs matching the ATL IRQ Mask AND or ATL IRQ Mask OR register bits combination. 0 -- No IRQ will be asserted because of completing ATL PTDs 1 -- IRQ will be asserted. For details, see Section 7.4.
7
INT_IRQ_E
INT IRQ Enable: Controls the IRQ assertion because of completing one or more INT PTDs matching the INT IRQ Mask AND or INT IRQ Mask OR register bits combination. 0 -- No IRQ will be asserted because of completing INT PTDs 1 -- IRQ will be asserted. For details, see Section 7.4.
6
CLKREADY_E Clock Ready Enable: Enables the IRQ assertion when internal clock signals are running stable. Useful after power-on or wake-up. 0 -- No IRQ will be generated after a CLKREADY_E event has occurred 1 -- IRQ will be generated after a CLKREADY_E event.
5
HCSUSP_E
Host Controller Suspend Enable: Enables the IRQ generation when the Host Controller enters suspend mode. 0 -- No IRQ will be generated because of the Host Controller entering suspend mode 1 -- IRQ will be generated at the Host Controller entering suspend mode.
4 3
DMAEOT INT_E
reserved; write logic 0 DMA EOT Interrupt Enable: Controls assertion of IRQ on the DMA transfer completion. 0 -- No IRQ will be generated after the DMA transfer is completed 1 -- IRQ will be asserted because of the DMA transfer completion.
2 to 1 0
-
reserved; write logic 0
SOFITLINT_E SOT ITL Interrupt Enable: Controls the IRQ generation at every SOF occurrence. 0 -- No IRQ will be generated on an SOF occurrence 1 -- IRQ will be asserted at every SOF.
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8.4.3 ISO IRQ MASK OR register (R/W: 0318h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. See Table 57 for bit description. For details, see Section 7.4.
Table 57: Bit 31 to 0 ISO IRQ MASK OR register: bit description Symbol Access Value 0000 0000h Description ISO IRQ Mask OR: Represents a direct map for ISO PTDs 31 to 0. 0 -- No OR condition defined between ISO PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain OR condition. ISO_IRQ_ R/W MASK_OR [31:0]
8.4.4 INT IRQ MASK OR register (R/W: 031Ch)
Each bit of this register (see Table 58) corresponds to one of the 32 INT PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.
Table 58: Bit 31 to 0 INT IRQ MASK OR register: bit description Symbol Access Value Description INT_IRQ_ R/W MASK_OR [31:0] 0000 0000h INT IRQ Mask OR: Represents a direct map for INT PTDs 31 to 0. 0 -- No OR condition defined between INT PTDs 31 to 0 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain OR condition.
8.4.5 ATL IRQ MASK OR register (R/W: 0320h)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a hardware IRQ mask for each PTD done map. See Table 59 for bit description. For details, see Section 7.4.
Table 59: Bit ATL IRQ MASK OR register: bit description Access Value R/W Description 0000 0000h ATL IRQ Mask OR: Represents a direct map for ATL PTDs 31 to 0. 0 -- No OR condition defined between the ATL PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain OR condition.
Symbol
31 to 0 ATL_IRQ_ MASK_OR [31:0]
8.4.6 ISO IRQ MASK AND register (R/W: 0324h)
Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4. Table 60 provides the bit description of the register.
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ISO IRQ MASK AND register: bit description Access Value R/W Description 0000 0000h ISO IRQ Mask AND: Represents a direct map for ISO PTDs 31 to 0. 0 -- No AND condition defined between ISO PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain AND condition between the 32 INT PTDs.
Table 60: Bit
Symbol
31 to 0 ISO_IRQ_ MASK_ AND[31:0]
8.4.7 INT IRQ MASK AND register (R/W: 0328h)
Each bit of this register (see Table 61) corresponds to one of the 32 INT PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4.
Table 61: Bit INT IRQ MASK AND register: bit description Access R/W Value Description 0000 0000h INT IRQ Mask AND: Represents a direct map for INT PTDs 31 to 0. 0 -- No OR condition defined between INT PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain AND condition between the 32 INT PTDs.
Symbol
31 to 0 INT_IRQ_ MASK_ AND[31:0]
8.4.8 ATL IRQ MASK AND register (R/W: 032Ch)
Each bit of this register corresponds to one of the 32 ATL PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Section 7.4. Table 62 shows the bit description of the register.
Table 62: Bit ATL IRQ MASK SAND register: bit description Access Value R/W 0000 0000h Description ATL IRQ Mask AND: Represents a direct map for ATL PTDs 31 to 0. 0 -- No OR condition defined between ATL PTDs 1 -- The bits corresponding to certain PTDs are set to logic 1 to define a certain AND condition between the 32 ATL PTDs.
Symbol
31 to 0 ATL_IRQ_ MASK_ AND[31:0]
8.5 Philips Transfer Descriptor
The standard EHCI data structures as described in Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 are optimized for the bus master operation that is managed by the hardware state machine. The PTD structures of the ISP1761 are translations of the EHCI data structures that are optimized for the ISP1761, while keeping the architecture of the EHCI data structures the same. This is because the ISP1761 is a slave Host Controller and has no bus master capability.
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EHCI manages schedules in two lists: periodic and asynchronous. The data structures are designed to provide the maximum flexibility required by USB, minimize memory traffic, and hardware and software complexity. The ISP1761 controller executes transactions for devices by using a simple shared-memory schedule. This schedule consists of data structures organized into three lists: qISO -- Isochronous transfer qINTL -- Interrupt transfer qATL -- Asynchronous transfer; for the control and bulk transfers. The system software maintains two lists for the Host Controller: periodic and asynchronous. The root of the periodic schedule--the PERIODICLISTBASE register--is the physical memory base address of the periodic frame list. The periodic frame list is an array memory pointer. The objects referenced from the frame list must be valid schedule data structures. The asynchronous list base is also a common list of queue heads (endpoints) that are served in a schedule. These endpoint data structures are further linked to the EHCI transfer descriptor that is the valid schedule (queue PTD). The Periodic Schedule Enable (ISO_BUF_FULL and INT_BUF_FULL) or Asynchronous Schedule Enable (ATL_BUF_FULL) bits can enable traversal to these lists. Enabling a list indicates the presence of valid schedule in the list. The system software starts at these points, schedules the first transfer inside the shared memory of the ISP1761, and sets up the ATL, INTL or ITL bit corresponding to the type of transfer scheduled in the shared memory. The ISP1761 has a maximum of 32 ISO, 32 INTL and 32 ATL PTDs. These PTDs are used as channels to transfer data from the shared memory to the USB bus. These channels are allocated and deallocated on receiving the transfer from the core USB driver. Multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by the EHCI data structure, until it reaches the terminate bit in a microframe. If a schedule is enabled, the Host Controller starts executing from the ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule. The EHCI periodic and asynchronous lists are traversed by the software according to the EHCI traversal rule, and executed only from the asynchronous schedule after it encounters the end of the periodic schedule. The Host Controller traverses the ISO, INTL and ATL schedules. It fetches the element and begins traversing the graph of linked schedule data structures. The last bit identifies the end of the schedule for each type of transfer, indicating the rest of the channels are empty. Once a transition is completed, the Host Controller executes from the next transfer descriptor in the schedule until the end of the microframe. The completion of a transfer is indicated to the software by the interrupt that can be grouped over the various PTDs by using the AND or OR registers that are available for each schedule type (ISO, INTL and ATL). These registers are simple logic registers to decide the group and individual PTDs that can interrupt the CPU for a schedule, when the logical conditions of the done bit is true in the shared memory that completes the interrupt. Interrupts are of four types and the latency can be programmed in multiples of SOF (125 s):
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* * * *
ISO interrupt INTL interrupt ATL Interrupt SOF--start of frame interrupt for the data transfer.
A static PTD that schedules inside the ISP1761 shared memory allows using the NextPTD mechanism that will enable the Host Controller driver to schedule the multiple PTDs that are of single endpoint and reduce the interrupt to the CPU. The NextPTD traversal rules defined by the ISP1761 hardware are: 1. Start the ATL header traversal. 2. If the current PTD is active and not done, perform the transaction. 3. Follow the next link pointer. 4. If PTD is not active and done, jump to the next PTD. 5. If the next link pointer is NULL, it means the end of the traversal.
START PTD SCHEDULE
follow the next link pointer
follow the next link pointer
no
PTD DONE?
yes
INCREMENT THE PTD horizontal link pointer EXECUTE THE PTD null pointer(1) END THE SCHEDULE END THE SCHEDULE
004aaa585
vertical link pointer EXECUTE THE PTD
(1) The NULL pointer terminates goes to the next link.
Fig 13. NextPTD traversal rule
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8.5.1 High-speed bulk IN and OUT, QHA
Table 63 shows the bit allocation of the high-speed bulk IN and OUT, Queue Head Asynchronous (QHA)1.
Table 63: Bit DW7 DW5 DW3 DW1 A H B X
[1]
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High-speed bulk IN and OUT, QHA: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved reserved P D T Cerr [1:0] reserved NakCnt[3:0] reserved S EP Type [1:0] 13 12 NrBytesTransferred[14:0] (32 kB for high-speed) Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt[3:0] 31 to 34 3 2 1 0
63
Bit DW6 DW4 DW2 DW0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5 J
4
reserved reserved reserved
[2]
NextPTDPointer[4:0] reserved
[1]
RL[3:0]
[1]
DataStartAddress[15:0] NrBytesToTransfer[14:0] (32 kB for high-speed)
Mult [1:0]
MaxPacketLength[10:0]
V
[1] [2]
Reserved. EndPt[0].
Hi-Speed USB OTG controller
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ISP1761
1.
Patent-pending: High-speed bulk IN and OUT, QHA.
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 64: Bit DW7 63 to 32 DW6 31 to 0 DW5 63 to 32 DW4 31 to 6 5
High-speed bulk IN and OUT, QHA: bit description Symbol reserved reserved reserved reserved J Access SW -- writes Description 0; not applicable for QHA. Jump: 0 -- To increment the PTD pointer 1 -- To enable the next PTD branching.
4 to 0 DW3 63 62 61
NextPTDPointer [4:0] A H B
SW -- writes
Next PTD Counter: Next PTD branching assigned by the PTD pointer.
SW -- sets HW -- resets HW -- writes HW -- writes
Active: Write the same value as that in V. Halt: This bit correspond to the Halt bit of the Status field of QH. Babble: This bit correspond to the Babble Detected bit in the Status field of the iTD, SiTD or QH. 1 -- When babbling is detected, A and V are set to 0. Error: This bit corresponds to the Transaction Error bit in the Status field of iTD, SiTD or QH (Exec_Trans, the signal name is xacterr). 0 -- No PID error. 1 -- If there are PID errors, this bit is set active. The A and V bits are also set to inactive. This transaction is retried three times.
60
X
HW -- writes
59 58
reserved P
HW -- writes
Ping: For high-speed transactions, this bit corresponds to the Ping state bit in the Status field of a QH. 0 -- Ping is not set. 1 -- Ping is set. Software sets this bit to 0.
57
DT
HW -- updates SW -- writes
Data Toggle: This bit is filled by software to start a PTD. If NrBytesToTransfer[14:0] is not complete, software needs to read this value and then write back the same value to continue. Error Counter. This field corresponds to the Cerr[1:0] field in QH. The default value of this field is zero for isochronous transactions. 00 -- The transaction will not retry. 11 -- The transaction will retry three times. Hardware will decrement these values. When the transaction has tried three times, X error will be updated.
56 to 55
Cerr[1:0]
HW -- writes SW -- writes
54 to 51
NakCnt[3:0]
HW -- writes SW -- writes
NAK Counter. This field corresponds to the NakCnt field in QH. Software writes for the initial PTD launch. The V bit is reset if NakCnt decrements to zero and RL is a non-zero value. It reloads from RL if transaction is ACKed. (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
50 to 47
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Table 64: Bit 46 to 32
High-speed bulk IN and OUT, QHA: bit description...continued Symbol Access Description Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. If Mult[1:0] is greater than one, it is possible to store intermediate results in this field. NrBytesTransferred HW -- writes [14:0] SW -- writes 0000 reserved RL[3:0] reserved DataStartAddress [15:0] SW -- writes SW -- writes
DW2 31 to 29 28 to 25 24 23 to 8 Set to 0 for QHA. Reload: If RL is set to 0h, hardware ignores the NakCnt value. RL and NakCnt are set to the same value before a transaction. Always 0 for QHA. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 7 to 0 DW1 63 to 47 46 reserved S SW -- writes Always 0 for QHA. This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction. 45 to 44 EPType[1:0] SW -- writes Transaction type: 00 -- Control 10 -- Bulk. 43 to 42 Token[1:0] SW -- writes Token: Identifies the token Packet Identifier (PID) for this transaction: 00 -- OUT 01 -- IN 10 -- SETUP 11 -- PING (written by hardware only). 41 to 35 34 to 32 DW0 31 30 to 29 EndPt[0] Mult[1:0] SW -- writes SW -- writes Endpoint: This is the USB address of the endpoint within the function. Multiplier: This field is a multiplier used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution. For QHA, this is a copy of the Async Schedule Park mode count, if the Async Schedule Park mode is enabled. These EHCI registers need to be set to reflect multiple cycles. Applicable for high-speed only. Set this field to 01b. You can also set it to 11b and 10b depending on your application. 00b is undefined. DeviceAddress[6:0] SW -- writes EndPt[3:1] SW -- writes Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. reserved -
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Table 64: Bit 28 to 18
High-speed bulk IN and OUT, QHA: bit description...continued Symbol MaxPacketLength [10:0] Access SW -- writes Description Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. The maximum packet size for a bulk transfer is 512 B. The maximum packet size for the isochronous transfer is also variable at any whole number. Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field (32 kB). Valid: 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
NrBytesToTransfer [14:0] reserved V
SW -- writes
2 to 1 0
SW -- sets HW -- resets
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8.5.2 High-speed isochronous IN and OUT, iTD
Table 65 shows the bit allocation of the high-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD)2.
Table 65: Bit DW7 DW5 DW3 DW1 A H B 63 High-speed isochronous IN and OUT, iTD: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 ISOIN_7[11:0] ISOIN_2[7:0] reserved reserved S EP Type [1:0] 13 12 ISOIN_1[11:0] Token [1:0] 11 10 9 ISOIN_6[11:0] ISOIN_5[7:0] ISOIN_0[11:0] NrBytesTransferred[14:0] (32 kB for high-speed) DeviceAddress[6:0] EndPt[3:0] 34 to 31 3 2 1 0
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Bit DW6 DW4 DW2 DW0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
ISOIN_5[3:0] Status7[2:0]
[2]
ISOIN_4[11:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] DataStartAddress[15:0] MaxPacketLength[10:0]
ISOIN_3[11:0] Status1[2:0] Status0[2:0]
ISOIN_2[3:0] SA[7:0] Frame[7:0]
[1]
Status6[2:0] reserved
Mult [1:0]
NrBytesToTransfer[14:0] (32 kB for high-speed)
V
[1] [2]
Reserved. EndPt[0].
Hi-Speed USB OTG controller
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
ISP1761
2.
Patent-pending: High-speed isochronous IN and OUT, iTD.
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 66: Bit DW7 63 to 52 51 to 40 39 to 32 DW6 31 to 28 27 to 16 15 to 4 3 to 0 DW5 63 to 56 55 to 44 43 to 32 DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8
High-speed isochronous IN and OUT, iTD: bit description Symbol ISOIN_7[11:0] ISOIN_6[11:0] ISOIN_5[7:0] Access HW -- writes HW -- writes HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 11 to 4), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 3 to 0), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 11 to 8), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. Bytes received during SOF0, if SA[0] is set to 1 and frame number is correct. ISO IN or OUT status at SOF7 ISO IN or OUT status at SOF6 ISO IN or OUT status at SOF5 ISO IN or OUT status at SOF4 ISO IN or OUT status at SOF3 ISO IN or OUT status at SOF2 ISO IN or OUT status at SOF1 Status of the payload on the USB bus for this SOF after ISO has been delivered. Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only).
ISOIN_5[3:0] ISOIN_4[11:0] ISOIN_3[11:0] ISOIN_2[3:0]
HW -- writes HW -- writes HW -- writes HW -- writes
ISOIN_2[7:0] ISOIN_1[11:0] ISOIN_0[11:0]
HW -- writes HW -- writes HW -- writes
Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0]
HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes
7 to 0
SA[7:0]
SW -- writes (0 => 1) HW -- writes (1 => 0) After processing
SOF Active: When the frame number of bits DW1[7:3] match the frame number of USB bus, these bits are checked for 1 before they are sent for SOF. For example: If SA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send ISO every SOF of the entire ms. If SA[7:0] = 0, 1, 0, 1, 0, 1, 0, 1: send ISO only on SOF0, SOF2, SOF4 and SOF6.
DW3 63 62 A H SW -- sets HW -- writes Active: This bit is the same as the Valid bit. Halt: Only one bit for the entire ms. When this bit is set, the Valid bit is reset. The device decides to stall an endpoint.
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Table 66: Bit 61 60 to 47 46 to 32
High-speed isochronous IN and OUT, iTD: bit description...continued Symbol B reserved Access HW -- writes Description Babble: Not applicable here. Set to 0 for isochronous. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. If Mult[1:0] is greater than one, it is possible to store intermediate results in this field. NrBytesTransferred[14:0] is 32 kB per PTD. Set to 0 for isochronous. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 Bits 2 to 0 -- Don't care Bits 7 to 3 -- Frame number that this PTD will be sent for ISO OUT or IN.
NrBytesTransferred HW -- writes [14:0]
DW2 31 to 24 23 to 8 reserved DataStartAddress [15:0] SW -- writes
7 to 0
Frame[7:0]
SW -- writes
DW1 63 to 47 46 reserved S SW -- writes This bit indicates whether a split transaction has to be executed. 0 -- High-speed transaction 1 -- Split transaction. 45 to 44 43 to 42 EPType[1:0] Token[1:0] SW -- writes SW -- writes Endpoint type: 01 -- Isochronous. Token: This field indicates the token PID for this transaction: 00 -- OUT 01 -- IN. 41 to 35 34 to 32 DW0 31 30 to 29 EndPt[0] Mult[1:0] SW -- writes SW -- writes Endpoint: This is the USB address of the endpoint within the function. This field is a multiplier counter used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution. For isochronous OUT and IN: If Mult[1:0] is 01 -- Data Toggle is Data0 If Mult[1:0] is 10 -- Data Toggle is Data1 If Mult[1:0] is 11 -- Data Toggle is Data2, and so on. For details, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, Appendix D. 28 to 18 MaxPacketLength [10:0] SW -- writes Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. The maximum packet size for an isochronous transfer is 1024 B. The maximum packet size for the isochronous transfer is also variable at any whole number. DeviceAddress[6:0] SW -- writes EndPt[3:1] SW -- writes Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function.
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ISP1761
Hi-Speed USB OTG controller
Table 66: Bit 17 to 3
High-speed isochronous IN and OUT, iTD: bit description...continued Symbol NrBytesToTransfer [14:0] reserved V Access SW -- writes Description Number of Bytes Transferred: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field (32 kB). 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
2 to 1 0
HW -- resets SW -- sets
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8.5.3 High-speed interrupt IN and OUT, QHP
Table 67 shows the bit allocation of the high-speed interrupt IN and OUT, Queue Head Periodic (QHP)3.
Table 67: Bit DW7 DW5 DW3 DW1 A H 63 High-speed interrupt IN and OUT, QHP: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 INT_IN_7[11:0] INT_IN_2[7:0] reserved D T Cerr [1:0] reserved INT_IN_1[11:0] reserved S EP Type [1:0] 13 12 INT_IN_6[11:0] INT_IN_5[7:0] INT_IN_0[11:0] NrBytesTransferred[14:0] (32 kB for high-speed) Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt[3:0] 31 to 34 3 2 1 0
Product data sheet Rev. 01 -- 12 January 2005 68 of 158
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Bit DW6 DW4 DW2 DW0
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
INT_IN_5[3:0] Status7[2:0]
[2]
INT_IN_4[11:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] DataStartAddress[15:0] MaxPacketLength[10:0]
INT_IN_3[11:0] Status1[2:0] Status0[2:0]
INT_IN_2[3:0] SA[7:0] Frame[7:0]
[1]
Status6[2:0] reserved
Mult [1:0]
NrBytesToTransfer[14:0] (32 kB for high-speed)
V
[1] [2]
Reserved. EndPt[0].
Hi-Speed USB OTG controller
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
ISP1761
3.
Patent-pending: High-speed interrupt IN and OUT, QHP.
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 68: Bit DW7 63 to 52 51 to 40 39 to 32 DW6 31 to 28 27 to 16 15 to 4 3 to 0 DW5 63 to 56 55 to 44 43 to 32 DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8
High-speed interrupt IN and OUT, QHP: bit description Symbol INT_IN_7[[11:0] INT_IN_6[11:0] INT_IN_5[7:0] Access HW -- writes HW -- writes HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 7 to 0), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF5 (bits 3 to 0), if SA[5] is set to 1 and frame number is correct. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 11 to 8), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. Bytes received during SOF0, if SA[0] is set to 1 and frame number is correct. INT OUT or IN Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0] HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes INT IN or OUT status of SOF7 INT IN or OUT status of SOF6 INT IN or OUT status of SOF5 INT IN or OUT status of SOF4 INT IN or OUT status of SOF3 INT IN or OUT status of SOF2 INT IN or OUT status of SOF1 Status of the payload on the USB bus for this SOF after INT has been delivered. Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only).
INT_IN_5[3:0] INT_IN_4[11:0] INT_IN_3[11:0] INT_IN_2[3:0]
HW -- writes HW -- writes HW -- writes HW -- writes
INT_IN_2[7:0] INT_IN_1[11:0] INT_IN_0[11:0]
HW -- writes HW -- writes HW -- writes
7 to 0
SA[7:0]
SW -- writes (0 => 1)
When the frame number of bits DW2[7:3] match the frame number of the USB bus, these bits are checked for 1 before they are sent for SOF. For example: When SA[7:0] = 1, 1, 1, 1, 1, 1, 1, 1: send INT for every SOF of HW -- writes the entire ms. When SA[7:0] = 0, 1, 0, 1, 0, 1, 0, 1: send INT for SOF0, (1 => 0) SOF2, SOF4 and SOF6. When SA[7:0] = 1, 0, 0, 0, 1, 0, 0, 0 = send After processing INT for every fourth SOF. HW -- writes SW -- writes Active: Write the same value as that in V.
DW3 63 A
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Hi-Speed USB OTG controller
Table 68: Bit 62 61 to 58 57
High-speed interrupt IN and OUT, QHP: bit description...continued Symbol H reserved DT Access HW -- writes HW -- writes SW -- writes Description Halt: Transaction is halted. Data Toggle: Set the Data Toggle bit to start the PTD. Software writes the current transaction toggle value. Hardware writes the next transaction toggle value. Error Counter: This field corresponds to the Cerr[1:0] field in the QH. The default value of this field is zero for isochronous transactions. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. If Mult[1:0] is greater than one, it is possible to store intermediate results in this field. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 Bits 7 to 3 represent the polling rate for ms-based polling. The INT polling rate is defined as 2(b - 1) SOF, where b is 1 to 9. When b is 1, 2, 3 or 4, use SA to define polling because the rate is equal to or less than 1 ms. Bits 7 to 3 are set to 0. Polling checks SA bits for SOF rates. b 1 2 3 4 5 6 7 8 9 Rate 1 SOF 2 SOF 4 SOF 1 ms 2 ms 4 ms 8 ms 16 ms 32 ms Frame[7:3] 0 0000 0 0000 0 0000 0 0000 0 0001 0 0010 to 0 0011 0 0100 to 0 0111 0 1000 to 0 1111 1 0000 to 1 1111 SA[7:0] 1111 1111 1010 1010 or 0101 0101 any 2 bits set any 1 bit set any 1 bit set any 1 bit set any 1 bit set any 1 bit set any 1 bit set
56 to 55 54 to 47 46 to 32
Cerr[1:0] reserved NrBytes Transferred [14:0] reserved DataStart Address [15:0] Frame[7:0]
HW -- writes SW -- writes HW -- writes
DW2 31 to 24 23 to 8 SW -- writes
7 to 0
SW -- writes
DW1 63 to 47 46 reserved S SW -- writes This bit indicates if a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction. 45 to 44 43 to 42 EPType[1:0] Token[1:0] SW -- writes SW -- writes Endpoint type: 11 -- Interrupt. Token: This field indicates the token PID for this transaction: 00 -- OUT 01 -- IN.
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ISP1761
Hi-Speed USB OTG controller
Table 68: Bit 41 to 35 34 to 32 DW0 31 30 to 29
High-speed interrupt IN and OUT, QHP: bit description...continued Symbol DeviceAddress [6:0] EndPt[3:1] EndPt[0] Mult[1:0] Access SW -- writes SW -- writes SW -- writes SW -- writes Description Device Address: This is the USB address of the function containing the endpoint that is referred to by the buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. Multiplier: This field is a multiplier counter used by the Host Controller as the number of successive packets the Host Controller may submit to the endpoint in the current execution. Set this field to 01b. You can also set it to 11b and 10b depending on your application. 00b is undefined.
28 to 18
MaxPacket Length[10:0] NrBytesTo Transfer[14:0] reserved V
SW -- writes
Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. Number of Bytes to Transfer: This field indicates the number of bytes can be transferred by this data structure. It is used to indicate the depth of the DATA field (32 kB). Valid: 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
SW -- writes
2 to 1 0
SW -- sets HW -- resets
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8.5.4 Start and complete split for bulk, QHA-SS/CS
Table 69 shows the bit allocation of start split and complete split for bulk, Queue Head Asynchronous Start Split and Complete Split (QHA-SS/CS)4.
Table 69: Bit DW7 DW5 DW3 DW1 A H B X S C
[1]
Product data sheet Rev. 01 -- 12 January 2005 72 of 158
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Start and complete split for bulk, QHASS/CS: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved reserved D T Cerr [1:0] NakCnt[3:0] PortNumber[6:0] reserved SE[1:0]
[1]
63
NrBytesTransferred[14:0] S EP Type [1:0] 13 12 Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt[3:0] (31 to 34) 3 2 1 0
HubAddress[6:0]
Bit DW6 DW4 DW2 DW0
[1] [2]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5 J
4
reserved reserved reserved
[2] [1]
NextPTDAddress[4:0] reserved
[1]
RL[3:0]
[1]
DataStartAddress[15:0] NrBytesToTransfer[14:0] (32 kB for high-speed)
MaxPacketLength[10:0]
V
Reserved. EndPt[0].
Hi-Speed USB OTG controller
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
ISP1761
4.
Patent-pending: Start and complete split for bulk, QHA-SS/CS.
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 70: Bit DW7 63 to 32 DW6 31 to 0 DW5 63 to 32 DW4 31 to 6 5 4 to 0 DW3 63 62 61
Start and complete split for bulk, QHASS/CS: bit description Symbol reserved reserved reserved reserved J NextPTDPointer [1:0] A H B Access SW -- writes SW -- writes Description 0 -- To increment the PTD pointer 1 -- To enable the next PTD branching. Next PTD Pointer: Next PTD branching assigned by the PTD pointer.
SW -- sets HW -- resets HW -- writes HW -- writes
Active: Write the same value as that in V. Halt: This bit correspond to the Halt bit of the Status field of QH. Babble: This bit correspond to the Babble Detected bit in the Status field of the iTD, SiTD or QH. 1 -- when babbling is detected, A and V are set to 0. Transaction Error: This bit corresponds to the Transaction Error bit in the status field.
60 59
X SC SW -- writes 0 HW -- updates
Start/Complete: 0 -- Start split 1 -- Complete split. Data Toggle: Set the Data Toggle bit to start for the PTD. Error Counter: This field contains the error count for start and complete split (QHASS). When an error has no response or bad response, Cerr[1:0] will be decremented to zero and then Valid will be set to zero. A NAK or NYET will reset Cerr[1:0]. For details, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, Section 4.12.1.2. If retry has insufficient time at the beginning of a new SOF, the first PTD must be this retry. This can be accomplished by if aperiodic PTD is not advanced.
58 57 56 to 55
reserved DT Cerr[1:0]
HW -- writes SW -- writes HW -- updates SW -- writes
54 to 51 50 to 47 46 to 32 DW2 31 to 29
NakCnt[3:0] reserved
HW -- writes SW -- writes -
NAK Counter: The V bit is reset if NakCnt decrements to zero and RL is a non-zero value. Not applicable to isochronous split transactions. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. -
NrBytesTransferred HW -- writes [14:0] reserved -
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Hi-Speed USB OTG controller
Table 70: Bit 28 to 25
Start and complete split for bulk, QHASS/CS: bit description...continued Symbol RL[3:0] Access SW -- writes Description Reload. If RL is set to 0h, hardware ignores the NakCnt value. Set RL and NakCnt to the same value before a transaction. For full-speed and low-speed transactions, set this field to 0000b. Not applicable to isochronous start split and complete split. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the direct CPU address. RAM address = (CPU address - 400h)/8 Hub Address: This indicates the hub address. Zero for the internal or embedded hub. Port Number: This indicates the port number of the hub or embedded TT. This depends on the endpoint type and direction. It is valid only for split transactions. The following applies to start split and complete split only. Bulk I/O I/O Control I/O I/O S 1 0 E 0 0 Remarks low-speed full-speed
24 23 to 8
reserved DataStartAddress [15:0]
SW -- writes
7 to 0 DW1 63 to 57 56 to 50 49 to 48
reserved HubAddress[6:0] PortNumber[6:0] SE[1:0]
SW -- writes SW -- writes SW -- writes
47 46
reserved S
SW -- writes
This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction.
45 to 44
EPType[1:0]
SW -- writes
Endpoint Type: 00 -- Control 10 -- Bulk.
43 to 42
Token[1:0]
SW -- writes
Token: This field indicates the PID for this transaction. 00 -- OUT 01 -- IN 10 -- SETUP.
41 to 35 34 to 32 DW0 31 30 to 29 28 to 18
DeviceAddress [6:0] EndPt[3:1] EndPt[0] reserved MaximumPacket Length[10:0]
SW -- writes SW -- writes SW -- writes SW -- writes
Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. The maximum packet size for full-speed is 64 B as defined in the Universal Serial Bus Specification Rev. 2.0.
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Hi-Speed USB OTG controller
Table 70: Bit 17 to 3
Start and complete split for bulk, QHASS/CS: bit description...continued Symbol NrBytesToTransfer [14:0] reserved V Access SW -- writes Description Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field. Valid: 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
2 to 1 0
SW -- sets HW -- resets
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8.5.5 Start and complete split for isochronous, SiTD
Table 71 shows the bit allocation for start and complete split for isochronous, Split isochronous Transfer Descriptor (SiTD)5.
Table 71: Bit DW7 DW5 DW3 DW1 A H ISO_IN_2[7:0] B X S C
[1]
Product data sheet Rev. 01 -- 12 January 2005 76 of 158
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Start and complete split for isochronous, SiTD: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved ISO_IN_1[7:0] D T PortNumber[6:0] reserved reserved S EP Type [1:0] 13 12 Token [1:0] 11 10 9 ISO_IN_0[7:0] ISO_IN_7[7:0] SCS[7:0] [2] NrBytesTransferred[11:0] DeviceAddress[6:0] EndPt[3:0] (31 to 34) 3 2 1 0
63
HubAddress[6:0]
Bit DW6 DW4 DW2 DW0
[1] [2] [3]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
ISO_IN_6[7:0] Status7 [2:0]
[3] [1]
ISO_IN_5[7:0] Status5 [2:0] Status4 [2:0] Status3 [2:0] Status2 [2:0]
ISO_IN_4[7:0] Status1 [2:0] Status0 [2:0]
ISO_IN_3[7:0] SA[7:0] Frame[7:0] (full-speed)
[1]
Status6 [2:0] reserved
DataStartAddress[15:0] TT_MPS_Len[10:0]
NrBytesToTransfer[14:0] (1 kB for full-speed)
V
Reserved. Note the change in the position of USCS[7:0] and NrBytesReceived_CS_IN. EndPt[0].
Hi-Speed USB OTG controller
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
ISP1761
5.
Patent-pending: Start and complete split for isochronous, SiTD.
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 72: Bit DW7 63 to 40 39 to 32 DW6 31 to 24 23 to 16 15 to 8 7 to 0 DW5 63 to 56 55 to 48 47 to 40 39 to 32
Start and complete split for isochronous, SiTD: bit description Symbol reserved ISO_IN_7[7:0] Access HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. Bytes received during SOF5, if SA[5] is set to 1 and frame number is correct. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. Bytes received during SOF0 if SA[0] is set to 1 and frame number is correct. All bits can be set to one for every transfer. It specifies which SOF the complete split needs to be sent. Valid only for IN. Start split (SS) and complete split (CS) active bits--SA = 0000 0001, S CS = 0000 0100--will cause SS to execute in Frame0 and CS in Frame2.
ISO_IN_6[7:0] ISO_IN_5[7:0] ISO_IN_4[7:0] ISO_IN_3[7:0]
HW -- writes HW -- writes HW -- writes HW -- writes
ISO_IN_2[7:0] ISO_IN_1[7:0] ISO_IN_0[7:0] SCS[7:0]
HW -- writes HW -- writes HW -- writes SW -- writes (0 => 1) HW -- writes (1 => 0) After processing
DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8 Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0] HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes Isochronous IN or OUT status of SOF7 Isochronous IN or OUT status of SOF6 Isochronous IN or OUT status of SOF5 Isochronous IN or OUT status of SOF4 Isochronous IN or OUT status of SOF3 Isochronous IN or OUT status of SOF2 Isochronous IN or OUT status of SOF1 Isochronous IN or OUT status of SOF0 Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only). 7 to 0 SA[7:0] SW -- writes (0 => 1) HW -- writes (1 => 0) After processing Specifies which SOF the start split needs to be placed. For OUT token: When the frame number of bits DW1(7-3) matches the frame number of the USB bus, these bits are checked for one before they are sent for the SOF. For IN token: Only SOF0, SOF1, SOF2 or SOF3 can be set to 1. Nothing can be set for SOF4 and above.
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Hi-Speed USB OTG controller
Table 72: Bit DW3 63 62 61 60 59
Start and complete split for isochronous, SiTD: bit description...continued Symbol A H B X SC Access SW -- sets HW -- resets HW -- writes HW -- writes HW -- writes SW -- writes 0 HW -- updates Halt: The Halt bit is set when any microframe transfer status has a stalled or halted condition. Babble: This bit corresponds to bit 1 of Status0 to Status7 for every microframe transfer status. Transaction Error: This bit corresponds to bit 0 of Status0 to Status7 for every microframe transfer status. Start/Complete: 0 -- Start split 1 -- Complete split. Data Toggle: Set the Data Toggle bit to start for the PTD. Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction. Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the CPU address. Bits 7 to 3 determine which frame to execute. Hub Address: This indicates the hub address. Zero for the internal or embedded hub. Port Number: This indicates the port number of the hub or embedded TT. Split: This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction. Description Active: Write the same value as that in V.
58 57 56 to 44 43 to 32 DW2 31 to 24 23 to 8
reserved DT reserved
HW -- writes SW -- writes -
NrBytesTransferred HW -- writes [11:0] reserved DataStartAddress [15:0] Frame[7:0] HubAddress [6:0] PortNumber [6:0] reserved S SW -- writes
7 to 0 DW1 63 to 57 56 to 50 49 to 47 46
SW -- writes SW -- writes SW -- writes SW -- writes
45 to 44 43 to 42
EPType[1:0] Token[1:0]
SW -- writes SW -- writes
Transaction type: 01 -- Isochronous. Token: Token PID for this transaction: 00 -- OUT 01 -- IN.
41 to 35 34 to 32 DW0 31 30 to 29
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Device Address[6:0] EndPt[3:1] EndPt[0] reserved
SW -- writes SW -- writes SW -- writes -
Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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ISP1761
Hi-Speed USB OTG controller
Table 72: Bit 28 to 18
Start and complete split for isochronous, SiTD: bit description...continued Symbol TT_MPS_Len [10:0] Access SW -- writes Description Transaction Translator Maximum Packet Size Length: This field indicates the maximum number of bytes that can be sent per start split depending on the number of total bytes needed. If the total bytes to be sent for the entire ms is greater than 188 B, this field should be set to 188 B for an OUT token and 192 B for an IN token. Otherwise, this field should be equal to the total bytes sent. Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field. This field is restricted to 1023 B because in SiTD the maximum allowable payload for a full-speed device is 1023 B. This field indirectly becomes the maximum packet size of the downstream device. 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
NrBytesTo Transfer[14:0]
SW -- writes
2 to 1 0
reserved V
SW -- sets HW -- resets
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8.5.6 Start and complete split for interrupt
Table 73 shows the bit allocation of start and complete split for interrupt6.
Table 73: Bit DW7 DW5 DW3 DW1 A H INT_IN_2[7:0] B X S C
[1]
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Start and complete split for interrupt: bit allocation 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 reserved INT_IN_1[7:0] D T Cerr [1:0] PortNumber[6:0] reserved SE[1:0] S EP Type [1:0] 13 12 INT_IN_0[7:0] INT_IN_7[7:0] SCS[7:0] NrBytesTransferred[11:0] (4 kB for full-speed and low-speed) Token [1:0] 11 10 9 DeviceAddress[6:0] EndPt [3:0] 3 2 1 0
63
HubAddress[6:0]
Bit DW6 DW4 DW2 DW0
[1] [2]
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
8
7
6
5
4
INT_IN_6[7:0] Status7 [2:0] Status6 [2:0] reserved
[2] [1]
INT_IN_5[7:0] Status5 [2:0] Status4 [2:0] Status3 [2:0] Status2 [2:0]
INT_IN_4[7:0] Status1 [2:0] Status0 [2:0]
INT_IN_3[7:0] SA[7:0] Frame[7:0] (full-speed and low-speed)
[1]
DataStartAddress[15:0] MaxPacketLength[10:0]
NrBytesToTransfer[14:0] (4 kB for full-speed and low-speed)
V
Reserved. EndPt[0].
Hi-Speed USB OTG controller
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ISP1761
6.
Patent-pending: Start and complete split for interrupt.
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
Table 74: Bit DW7 63 to 40 39 to 32 DW6 31 to 24 23 to 16 15 to 8 7 to 0 DW5 63 to 56
Start and complete split for interrupt: bit description Symbol reserved INT_IN_7[7:0] Access HW -- writes Description Bytes received during SOF7, if SA[7] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF6, if SA[6] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF5, if SA[5] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF4, if SA[4] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF3, if SA[3] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF2 (bits 7 to 0), if SA[2] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF1, if SA[1] is set to 1 and frame number is correct. The new value continuously overwrites the old value. Bytes received during SOF0 if SA[0] is set to 1 and frame number is correct. The new value continuously overwrites the old value.
INT_IN_6[7:0] INT_IN_5[7:0] INT_IN_4[7:0] INT_IN_3[7:0]
HW -- writes HW -- writes HW -- writes HW -- writes
INT_IN_2[7:0]
HW -- writes
55 to 48 47 to 40 39 to 32
INT_IN_1[7:0] INT_IN_0[7:0] SCS[7:0]
HW -- writes HW -- writes
SW -- writes (0 => 1) All bits can be set to one for every transfer. It specifies which SOF the complete split needs to be sent. Valid only for IN. Start split (SS) and HW -- writes complete split (CS) active bits--SA = 0000 0001, S CS = 0000 (1 => 0) 0100--will cause SS to execute in Frame0 and CS in Frame2. After processing HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes HW -- writes Interrupt IN or OUT status of SOF7 Interrupt IN or OUT status of SOF6 Interrupt IN or OUT status of SOF5 Interrupt IN or OUT status of SOF4 Interrupt IN or OUT status of SOF3 Interrupt IN or OUT status of SOF2 Interrupt IN or OUT status of SOF1 Interrupt IN or OUT status of SOF0 Bit 0 -- Transaction Error (IN and OUT) Bit 1 -- Babble (IN token only) Bit 2 -- underrun (OUT token only).
DW4 31 to 29 28 to 26 25 to 23 22 to 20 19 to 17 16 to 14 13 to 11 10 to 8 Status7[2:0] Status6[2:0] Status5[2:0] Status4[2:0] Status3[2:0] Status2[2:0] Status1[2:0] Status0[2:0]
7 to 0
SA[7:0]
SW -- writes (0 => 1) Specifies which SOF the start split needs to be placed. HW -- writes (1 => 0) After processing For OUT token: When the frame number of bits DW1(7-3) matches the frame number of the USB bus, these bits are checked for one before they are sent for the SOF. For IN token: Only SOF0, SOF1, SOF2 or SOF3 can be set to 1. Nothing can be set for SOF4 and above.
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Table 74: Bit DW3 63 62 61 60 59
Start and complete split for interrupt: bit description...continued Symbol A H B X SC Access SW -- sets HW -- resets HW -- writes HW -- writes HW -- writes SW -- writes 0 HW -- updates Halt: The Halt bit is set when any microframe transfer status has a stalled or halted condition. Babble: This bit corresponds to bit 1 of Status0 to Status7 for every microframe transfer status. Transaction Error: This bit corresponds to bit 0 of Status0 to Status7 for every microframe transfer status. Start/Complete: 0 -- Start split 1 -- Complete split. Data Toggle: For an interrupt transfer, set correct bit to start the PTD. Error Counter: This field corresponds to the Cerr[1:0] field in QH. 00 -- The transaction will not retry. 11 -- The transaction will retry three times. Hardware will decrement these values. When the transaction has tried three times, X error will be updated. Description Active: Write the same value as that in V.
58 57 56 to 55
reserved DT Cerr[1:0]
HW -- writes SW -- writes HW -- writes SW -- writes
54 to 44 43 to 32
reserved NrBytes Transferred [11:0] reserved DataStart Address[15:0] Frame[7:0]
HW -- writes
Number of Bytes Transferred: This field indicates the number of bytes sent or received for this transaction.
DW2 31 to 24 23 to 8 SW -- writes Data Start Address: This is the start address for the data that will be sent or received on or from the USB bus. This is the internal memory address and not the CPU address. Bits 7 to 3 is the ms polling rate. Polling rate is defined as 2(b - 1) SOF; where b = 4 to 16. When b is 4, every ms is executed. b 5 6 7 8 9 DW1 63 to 57 56 to 50 HubAddress [6:0] PortNumber [6:0] SW -- writes SW -- writes Hub Address: This indicates the hub address. Zero for the internal or embedded hub. Port Number: This indicates the port number of the hub or embedded TT. Rate 2 ms 4 ms 8 ms 16 ms 32 ms Frame[7:3] 0 0001 0 0010 or 0 0011 0 0100 or 0 0111 0 1000 or 0 1111 1 0000 or 1 1111
7 to 0
SW -- writes
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Table 74: Bit 49 to 48
Start and complete split for interrupt: bit description...continued Symbol SE[1:0] Access SW -- writes Description This depends on the endpoint type and direction. It is valid only for split transactions. The following applies to start split and complete split only. Interrupt I/O I/O S 1 0 E 0 0 Remarks low-speed full-speed
47 46
reserved S
SW -- writes
This bit indicates whether a split transaction has to be executed: 0 -- High-speed transaction 1 -- Split transaction.
45 to 44 43 to 42
EPType[1:0] Token[1:0]
SW -- writes SW -- writes
Transaction type: 11 -- Interrupt. Token PID for this transaction: 00 -- OUT 01 -- IN.
41 to 35 34 to 32 DW0 31 30 to 29 28 to 18
DeviceAddress [6:0] EndPt[3:1] EndPt[0] reserved MaxPacket Length[10:0]
SW -- writes SW -- writes SW -- writes SW -- writes
Device Address: This is the USB address of the function containing the endpoint that is referred to by this buffer. Endpoint: This is the USB address of the endpoint within the function. Endpoint: This is the USB address of the endpoint within the function. Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet. The maximum packet size for the full-speed and low-speed devices is 64 B as defined in the Universal Serial Bus Specification Rev. 2.0. Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure. It is used to indicate the depth of the DATA field. The maximum total number of bytes for this transaction is 4 kB. 0 -- This bit is deactivated when the entire PTD is executed--across SOF and SOF--or when a fatal error is encountered. 1 -- Software updates to one when there is payload to be sent or received even across ms boundary. The current PTD is active.
17 to 3
NrBytesTo Transfer[14:0]
SW -- writes
2 to 1 0
reserved V
SW -- sets HW -- resets
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9. OTG Controller
9.1 Introduction
OTG is a supplement to the Hi-Speed USB specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals. It is primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. Non-portable devices--even standard hosts--can also benefit from OTG features. The ISP1761 OTG controller is designed to perform all the tasks specified in the OTG supplement. It supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The ISP1761 uses software implementation of HNP and SRP for maximum flexibility. A set of OTG registers provides the control and status monitoring capabilities to support software HNP and SRP. Besides the normal USB transceiver, timers and analog components required by OTG are also integrated on-chip. The analog components include:
* * * *
Built-in 3.3 V-to-5 V charge pump Voltage comparators Pull-up or pull-down resistors on data lines Charging or discharging resistors for VBUS.
9.2 Dual-role device
When port 1 of the ISP1761 is configured in the OTG mode, it can be used as an OTG dual-role device. A dual-role device is a USB device that can function either as a host or as a peripheral. The default role of the ISP1761 is controlled by the ID pin, which in turn is controlled by the type of plug connected to the mini-AB receptacle. If ID = LOW (mini-A plug connected), it becomes an A-device, which is a host by default. If ID = HIGH (mini-B plug connected), it becomes a B-device, which is a peripheral by default. Both the A-device and the B-device work on a session base. A session is defined as the period of time in which devices exchange data. A session starts when VBUS is driven and ends when VBUS is turned off. Both the A-device and the B-device may start a session. During a session, the role of the host can be transferred back and forth between the A-device and the B-device any number of times by using HNP. If the A-device wants to start a session, it turns on VBUS by enabling the charge pump. The B-device detects that VBUS has risen above the B_SESS_VLD level and assumes the role of a peripheral asserting its pull-up resistor on the DP line. The A-device detects the remote pull-up resistor and assumes the role of a host. Then, the A-device can communicate with the B-device as long as it wishes. When the A-device finishes communicating with the B-device, the A-device turns-off VBUS and both the devices finally go into the idle state. See Figure 15 and Figure 16. If the B-device wants to start a session, it must initiate SRP by `data line pulsing' and `VBUS pulsing'. When the A-device detects any of these SRP events, it turns on its VBUS. (Note: only the A-device is allowed to drive VBUS.) The B-device assumes the role of a
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peripheral, and the A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device. The A-device will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into the suspend state. The B-device signals claiming the host role by deasserting its pull-up resistor. The A-device acknowledges by going into the peripheral state. The B-device then assumes the role of a host and communicates with the A-device as long as it wishes. When the B-device finishes communicating with the A-device, both the devices finally go into the idle state. See Figure 15 and Figure 16.
9.3 Session Request Protocol (SRP)
As a dual-role device, the ISP1761 can initiate and respond to SRP. The B-device initiates SRP by data line pulsing, followed by VBUS pulsing. The A-device can detect either data line pulsing or VBUS pulsing.
9.3.1 B-device initiating SRP
The ISP1761 can initiate SRP by performing the following steps: 1. Detect initial conditions [read B_SESS_END and B_SE0_SRP (bits 7 and 8) of the OTG Status register]. 2. Start data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (set) register to logic 1]. 3. Wait for 5 ms to 10 ms. 4. Stop data line pulsing [set DP_PULLUP (bit 0) of the OTG Control (clear) register to logic 0]. 5. Start VBUS pulsing [set VBUS_CHRG (bit 6) of the OTG Control (set) register to logic 1]. 6. Wait for 10 ms to 20 ms. 7. Stop VBUS pulsing [set VBUS_CHRG (bit 6) of the OTG Control (clear) register to logic 0]. 8. Discharge VBUS for about 30 ms [by using VBUS_DISCHRG (bit 5) of the OTG Control (set) register], optional. The B-device must complete both data line pulsing and VBUS pulsing within 100 ms.
9.3.2 A-device responding to SRP
The A-device must be able to respond to one of the two SRP events: data line pulsing or VBUS pulsing. When data line pulsing is used, the ISP1761 can detect DP pulsing. This means that the peripheral-only device must initiate data line pulsing through DP. A dual-role device will always initiate data line pulsing through DP. To enable the SRP detection through the VBUS pulsing, set A_B_SESS_VLD (bit 1) in the OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers. To enable the SRP detection through the DP pulsing, set DP_SRP (bit 2) in the OTG Interrupt Enable Rise register.
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9.4 Host Negotiation Protocol (HNP)
HNP is used to transfer control of the host role between the default host (A-device) and the default peripheral (B-device) during a session. When the A-device is ready to give up its role as a host, it will condition the B-device using SetFeature (b_hnp_enable) and will go into suspend. If the B-device wants to use the bus at that time, it signals a disconnect to the A-device. Then, the A-device will take the role of a peripheral and the B-device will take the role of a host.
9.4.1 Sequence of HNP events
The sequence of events for HNP as observed on the USB bus is illustrated in Figure 14.
A-device 1 3 B-device 2 5 4 7 6 8
DP Composite
004aaa079
Legend
DP driven Pull-up dominates Pull-down dominates Normal bus activity
Fig 14. HNP sequence of events
As can be seen in Figure 14: 1. The A-device completes using the bus and stops all bus activity, that is, suspends the bus. 2. The B-device detects that the bus is idle for more than 5 ms and begins HNP by turning off the pull-up on DP. This allows the bus to discharge to the SE0 state. 3. The A-device detects SE0 on the bus and recognizes this as a request from the B-device to become a host. The A-device responds by turning on its DP pull-up within 3 ms of first detecting SE0 on the bus. 4. After waiting for 30 s to ensure that the DP line is not HIGH because of the residual effect of the B-device pull-up, the B-device notices that the DP line is HIGH and the DM line is LOW (that is, J state). This indicates that the A-device has recognized the HNP request from the B-device. At this point, the B-device becomes a host and asserts bus reset to start using the bus. The B-device must assert the bus reset (that is, SE0) within 1 ms of the time that the A-device turns on its pull-up. 5. When the B-device completes using the bus, it stops all bus activities. Optionally, the B-device may turn on its DP pull-up at this time. 6. The A-device detects lack of bus activity for more than 3 ms and turns off its DP pull-up. Alternatively, if the A-device has no further need to communicate with the B-device, the A-device may turn off VBUS and end the session.
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7. The B-device turns on its pull-up. 8. After waiting 30 s to ensure that the DP line is not HIGH because of the residual effect of the A-device pull-up, the A-device notices that the DP-line is HIGH and the DM line is LOW, indicating that the B-device is signaling a connect and is ready to respond as a peripheral. At this point, the A-device becomes a host and asserts the bus reset to start using the bus.
9.4.2 OTG state diagrams
Figure 15 and Figure 16 show the state diagrams for the dual-role A-device and the dual-role B-device, respectively. For a detailed explanation, refer to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a. The OTG state machine is implemented with software. The inputs to the state machine come from four sources: hardware signals from the USB bus, software signals from the application program, internal variables with the state machines, and timers:
* Hardware inputs: Include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end,
a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume, b_bus_resume, a_srp_det and b_se0_srp. All these inputs can be derived from the OTG Interrupt and OTG Status registers.
* Software inputs: Include a_bus_req, a_bus_drop and b_bus_req. * Internal variables: Include a_set_b_hnp_en, b_hnp_enable and b_srp_done. * Timers: The HNP state machine uses four timers: a_wait_vrise_tmr,
a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on entry to and reset on exit from their associated states. The ISP1761 provides a programmable timer that can be used as any of these four timers.
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START a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id
b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/
id | a_bus_req | (a_sess_vld/ & b_conn/)
a_bus_drop/ & (a_bus_req | a_srp_det)
a_wait_vfall drv_vbus/ loc_conn/ loc_sof/ id | a_bus_drop
id | a_bus_drop | a_wait_bcon_tmout
a_wait_vrise drv_vbus loc_conn/ loc_sof/
b_bus_suspend
id | a_bus_drop
a_vbus_err drv_vbus/ loc_conn/ loc_sof/ a_vbus_vld/ a_vbus_vld/
id | a_bus_drop | a_vbus_vld | a_wait_vrise_tmout
a_peripheral drv_vbus loc_conn loc_sof/
a_vbus_vld/
a_vbus_vld/
a_wait_bcon drv_vbus loc_conn/ loc_sof/
b_conn/ & a_set_b_hnp_en/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_bus_req | b_bus_resume a_suspend drv_vbus loc_conn/ loc_sof/ a_bus_req/ | a_suspend_req a_host drv_vbus loc_conn/ loc_sof
id | b_conn/ | a_bus_drop
b_conn
004aaa566
Fig 15. Dual-role A-device state diagram
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START b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id/
a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ b_bus_req & b_sess_end & b_se0_srp
id/ | b_sess_vld/
id/ | b_srp_done b_host chrg_vbus/ loc_conn/ loc_sof id/ | b_sess_vld/ id/ | b_sess_vld/ b_srp_init pulse loc_conn pulse chrg_vbus loc_sof/
b_sess_vld a_conn b_bus_req/ | a_conn/
a_bus_resume | b_ase0_brst_tmout b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ b_peripheral chrg_vbus/ loc_conn loc_sof/
004aaa567
b_bus_req & b_hnp_en & a_bus_suspend
Fig 16. Dual-role B-device state diagram
9.4.3 HNP implementation and OTG state machine
The OTG state machine is the software behind all the OTG functionality. It is implemented in the microprocessor system that is connected to the ISP1761. The ISP1761 provides registers for all input status, the output control and timers to fully support the state machine transitions in Figure 15 and Figure 16. These registers include:
* OTG Control register: Provides control to VBUS driving, charging or discharging, data
line pull-up or pull-down, SRP detection and so on.
* OTG Status register: Provides status detection on VBUS and data lines including ID,
VBUS session valid, session end, overcurrent and bus status.
* OTG Interrupt Latch register: Provides interrupts for status change in OTG Interrupt
Status register bits and the OTG Timer time-out event.
* OTG Interrupt Enable Fall and OTG Interrupt Enable Rise registers: Provide interrupt
mask for OTG Interrupt Latch register bits.
* OTG Timer register: Provides 0.01 ms base programmable timer for use in the OTG
state machine. The following steps are required to enable an OTG interrupt: 1. Set the polarity and the level-triggering or edge-triggering mode of the HW Mode Control register.
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2. Set the corresponding bits of the OTG Interrupt Enable Rise and OTG Interrupt Enable Fall registers. 3. Set bit OTG_IRQ_E of the HcInterruptEnable register (bit 10). 4. Set bit GLOBAL_INTR_EN of the HW Mode Control register (bit 0). When an interrupt is generated on HC_IRQ, perform these steps in the interrupt service routine to get the related OTG status: 1. Read the HcInterrupt register. If OTG_IRQ (bit 10) is set, then step 2. 2. Read the OTG Interrupt Latch register. If any of the bits 0 to 4 are set, then step 3. 3. Read the OTG Status register. The OTG state machine routines are called when any of the inputs is changed. These inputs come from either OTG registers (hardware) or application program (software). The outputs of the state machine include control signals to the OTG register (for hardware) and states or error codes (for software). The ISP1761 can be configured in OTG mode or in pure host or peripheral mode. Programming the ISP1761 in OTG mode is done by setting bit 10 of the OTG control register. This will enable OTG-specific mechanisms controlled by the OTG control register bits. When the OTG protocol is not implemented by the software, the ISP1761 can be used as a host or a peripheral. In this case, bit 10 of the OTG control register will be set to logic 0. The host or peripheral functionality is determined by bit 7 of the OTG Control register. Programming of the OTG registers is done by a SET and RESET scheme. An OTG register has two parts: a 16-bit SET and a 16-bit RESET. Writing logic 1 in a certain position to the SET-type dedicated 16-bit register part will set the respective bit to logic 1 while writing logic 1 to the RESET-type 16-bit dedicated register will change the corresponding bit to logic 0.
9.5 OTG Controller registers
Table 75: Address 037Xh--038Xh Table 76: Address 0370h 0374h 0378h 037Ch 0380h 0384h
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OTG Controller-specific register overview Register OTG registers Reset value References -
Address mapping of registers: 32-bit data bus mode Byte 3 Byte 2 Byte 1 Byte 0
Device ID registers Product ID (read only) OTG Control (clear) reserved OTG Interrupt Latch (clear) OTG Interrupt Enable Fall (clear) OTG Interrupt Enable Rise (clear) Vendor ID (read only) OTG Control (set) OTG Status (read only) OTG Interrupt Latch (set) OTG Interrupt Enable Fall (set) OTG Interrupt Enable Rise (set)
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OTG Control register OTG Interrupt registers
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Address mapping of registers: 32-bit data bus mode...continued Byte 3 Byte 2 Byte 1 Byte 0
Table 76: Address 0388h 038Ch Table 77: Address 0370h 0372h 0374h 0376h 0378h 037Ah 037Ch 037Eh 0380h 0382h 0384h 0386h 0388h 038Ah 038Ch 038Eh
OTG Timer register OTG Timer (Lower word--clear) OTG Timer (Higher word--clear) OTG Timer (Lower word--set) OTG Timer (Higher word--set)
Address mapping of registers: 16-bit data bus mode Byte 1 Byte 0 Reference Section 9.5.1.1 on page 91 Section 9.5.1.2 on page 91 Section 9.5.2.1 on page 92
Device ID registers Vendor ID (read only) Product ID (read only) OTG Control (set) OTG Control (clear) OTG Status (read only) reserved OTG Interrupt Latch (set) OTG Interrupt Latch (clear) OTG Interrupt Enable Fall (set) OTG Interrupt Enable Fall (clear) OTG Interrupt Enable Rise (set) OTG Interrupt Enable Rise (clear) OTG Timer (Lower word--set) OTG Timer (Lower word--clear) OTG Timer (Higher word--set) OTG Timer (Higher word--clear) Section 9.5.4.1 on page 96 Section 9.5.3.4 on page 95 Section 9.5.3.3 on page 95 Section 9.5.3.1 on page 93 Section 9.5.3.2 on page 94
OTG Control register
OTG Interrupt registers
OTG Timer register
9.5.1 Device Identification registers
9.5.1.1 Vendor ID register (R: 0370h) Table 78 shows the bit description of the register.
Table 78: Bit 15 to 0 Vendor ID register: bit description Symbol VENDOR_ID[15:0] Access R Value 04CCh Description Philips Semiconductors' Vendor ID
9.5.1.2
Product ID register (R: 0372h) The bit description of the register is given in Table 79.
Table 79: Bit 15 to 0 Product ID register: bit description Symbol PRODUCT_ID[15:0] Access R Value 1761h Description Product ID of the ISP1761
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9.5.2 OTG Control register
9.5.2.1 OTG Control register (S/C: 0374h/0376h) Table 80 shows the bit allocation of the register.
Table 80: Bit Symbol Reset Access Bit Symbol Reset Access
[1]
OTG Control register: bit allocation 15 14 13 reserved [1] 0 R/S/C 7 SW_SEL_ HC_DC 1 R/S/C 0 R/S/C 6 VBUS_ CHRG 0 R/S/C 0 R/S/C 5 VBUS_ DISCHRG 0 R/S/C 0 R/S/C 4 VBUS_ DRV 0 R/S/C 0 R/S/C 3 SEL_CP_ EXT 0 R/S/C 12 11 10 OTG_ DISABLE 0 R/S/C 2 DM_PULL DOWN 1 R/S/C 9 OTG_SE0_ EN 0 R/S/C 1 DP_PULL DOWN 1 R/S/C 8 BDIS_ ACON_EN 0 R/S/C 0 DP_ PULLUP 0 R/S/C
The reserved bits should always be written with the reset value.
Table 81: Bit [1] 10 9 15 to 11 -
OTG Control register: bit description Symbol OTG_DISABLE OTG_SE0_EN Description reserved for future use 0 -- OTG functionality enabled 1 -- OTG disabled; pure host or peripheral. This bit is used by the Host Controller to send SE0 on remote connect. 0 -- No SE0 sent on remote connect detection 1 -- SE0 (bus reset) sent on remote connect detection. Remark: This bit is normally set when the B-device goes into the B_WAIT_ACON state (recommended sequence: LOC_CONN = 0 -> DELAY -> 0 ms -> OTG_SEQ_EN = 1 -> SEL_HC_DC = 0) and is cleared when it comes out of the B_WAIT_ACON state.
8 7
BDIS_ACON_EN SW_SEL_HC_ DC
Enables the A-device to connect if the B-device disconnect is detected In the software HNP mode, this bit selects between the Host Controller and the Peripheral Controller. 0 -- Host Controller connected to ATX 1 -- Peripheral Controller connected to ATX. This bit is set to logic 1 by hardware when there is an event corresponding to the BDIS_ACON interrupt (BDIS_ACON_EN is set and there is an automatic pull-up connection on remote disconnect).
6 5 4 3
VBUS_CHRG VBUS_DRV SEL_CP_EXT
Connect VBUS to VCC(I/O) through a resistor Drive VBUS to 5 V using the charge pump 0 -- internal charge pump selected 1 -- external charge pump selected.
VBUS_DISCHRG Discharge VBUS to ground through a resistor
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OTG Control register: bit description...continued Symbol Description 0 -- Disable 1 -- Enable. DM_PULLDOWN DM pull down:
Table 81: Bit [1] 2
1
DP_PULLDOWN
DP pull down: 0 -- Disable 1 -- Enable.
0
DP_PULLUP
0 -- The pull-up resistor is disconnected from the DP line. The data line pulsing is stopped. 1 -- An internal 1.5 k pull-up resistor is present on the DP line. The data line pulsing is started. Remark: When port 1 is in the peripheral mode or it plays the role of a peripheral while the OTG functionality is enabled, it depends on the setting of DP_PULLUP and the VBUS sensing signal to connect the DP line to HIGH through a pull-up resister. (VBUS is an internal signal. When 5 V is present on the VBUS pin, VBUS = 1.).
[1]
To use port 1 as a Host Controller, write 0080 0018h to this register after power on. To use port 1 as a Peripheral Controller, write 0006 0400h to this register after power on.
9.5.3 OTG Interrupt registers
9.5.3.1 OTG Status register (R: 0378h) This register indicates the current state of the signals that can generate an interrupt. The bit allocation of the register is given in Table 82.
Table 82: Bit Symbol Reset Access Bit Symbol Reset Access
[1]
OTG Status register: bit allocation 15 14 13 reserved 0 R 7 B_SESS_ END
[1]
12
11
10 OTG_ SUSPEND
9 reserved 0 R 1
8 B_SE0_ SRP 0 R 0
0 R 6 reserved 0 R
0 R 5
0 R 4 RMT_ CONN
0 R 3 ID
[1]
0 R 2 DP_SRP 0 R
A_B_SESS VBUS_VLD _VLD
[1] [1]
0 R
0 R
R
R
R
R
The reset value depends on the corresponding OTG status. For details, see Table 83.
Table 83: Bit 15 to 11 10 9 8
OTG Status register: bit description Symbol OTG_SUSPEND B_SE0_SRP Description reserved for future use Indicates that the bus is idle for > 3 ms reserved 2 ms of SE0 detected in the B-idle state
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OTG Status register: bit description...continued Symbol B_SESS_END RMT_CONN ID DP_SRP A_B_SESS_VLD VBUS_VLD Description VBUS < 0.8 V reserved Remote connect detection ID pin digital input DP asserted during SRP A session valid for the A-device. B session valid for the B-device. A-device VBUS valid comparator, indicates VBUS > 4.4 V
Table 83: Bit 7 6 to 5 4 3 2 1 0
9.5.3.2
OTG Interrupt Latch register (S/C: 037Ch/037Eh) The OTG Interrupt Latch register indicates the source that generated the interrupt. The status of this register bits depends on the settings of the Interrupt Enable Fall and Interrupt Enable Rise registers, and the occurrence of the respective events. The bit allocation of the register is given in Table 84.
Table 84: Bit Symbol Reset Access Bit Symbol Reset Access
[1]
OTG Interrupt Latch register: bit allocation 15 14 13 reserved [1] 0 R/S/C 7 B_SESS_ END 0 R/S/C 0 R/S/C 6 BDIS_ ACON 0 R/S/C 0 R/S/C 5 OTG_ RESUME 0 R/S/C 0 R/S/C 4 RMT_ CONN 0 R/S/C 0 R/S/C 3 ID 0 R/S/C 12 11 10 OTG_ SUSPEND 0 R 2 DP_SRP 0 R/S/C 9 OTG_TMR _TIMEOUT 0 R/S/C 1 8 B_SE0_ SRP 0 R/S/C 0
A_B_SESS VBUS_VLD _VLD 0 R/S/C 0 R/S/C
The reserved bits should always be written with the reset value.
Table 85: Bit 15 to 11 10 9 8 7 6 5 4 3 2 1 0
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OTG Interrupt Latch register: bit description Symbol OTG_SUSPEND B_SE0_SRP B_SESS_END BDIS_ACON OTG_RESUME RMT_CONN ID DP_SRP A_B_SESS_VLD VBUS_VLD Description reserved for future use Indicates that the bus is idle for > 3 ms 2 ms of SE0 detected in the B-idle state VBUS < 0.8 V Indicates that the BDIS_ACON event has occurred J -> K resume change detected Remote connect detection Indicates change on pin ID DP asserted during SRP A-session valid for the A-device. B session valid for the B-device. Indicates change in the VBUS_VLD status
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OTG_TMR_TIMEOUT OTG timer timeout
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9.5.3.3
OTG Interrupt Enable Fall register (S/C: 0380h/0382h) Table 86 shows the bit allocation of this register that enables interrupts on transition from HIGH-to-LOW.
Table 86: Bit Symbol Reset Access Bit Symbol Reset Access
[1]
OTG Interrupt Enable Fall register: bit allocation 15 14 13 reserved [1] 0 R/S/C 7 B_SESS_ END 0 R/S/C 0 R/S/C 0 R/S/C 6 reserved 0 R/S/C 0 R/S/C 5 0 R/S/C 4 RMT_ CONN 0 R/S/C 0 R/S/C 3 ID 0 R/S/C 12 11 10 OTG_ SUSPEND 0 R 2 reserved 0 R/S/C 9 reserved 0 R/S/C 1 8 B_SE0_ SRP 0 R/S/C 0
A_B_SESS VBUS_VLD _VLD 0 R/S/C 0 R/S/C
The reserved bits should always be written with the reset value.
Table 87: Bit 15 to 11 10 9 8 7 6 to 5 4 3 2 1 0
OTG Interrupt Enable Fall register: bit description Symbol OTG_SUSPEND B_SE0_SRP B_SESS_END RMT_CONN ID A_B_SESS_VLD VBUS_VLD Description reserved for future use IRQ asserted when the bus exits from the idle state reserved IRQ asserted when the bus exits from at least 2 ms of the SE0 state IRQ asserted when VBUS > 0.8 V reserved IRQ asserted on RMT_CONN removal IRQ asserted on the ID pin transition from HIGH to LOW reserved IRQ asserted on removing A-session valid for the A-device or B-session valid for the B-device condition IRQ asserted on the falling edge of VBUS
9.5.3.4
OTG Interrupt Enable Rise register (S/C: 0384h/0386h) This register (see Table 88 for bit allocation) enables interrupts on transition from LOW-to-HIGH.
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Table 88: Bit Symbol Reset Access Bit Symbol Reset Access
[1]
OTG Interrupt Enable Rise register: bit allocation 15 14 13 reserved [1] 0 R/S/C 7 B_SESS_ END 0 R/S/C 0 R/S/C 6 BDIS_ ACON 0 R/S/C 0 R/S/C 5 OTG_ RESUME 0 R/S/C 0 R/S/C 4 RMT_ CONN 0 R/S/C 0 R/S/C 3 ID 0 R/S/C 12 11 10 OTG_ SUSPEND 0 R 2 DP_SRP 0 R/S/C 9 OTG_TMR _TIMEOUT 0 R/S/C 1 8 B_SE0_ SRP 0 R/S/C 0
A_B_SESS VBUS_VLD _VLD 0 R/S/C 0 R/S/C
The reserved bits should always be written with the reset value.
Table 89: Bit 15 to 11 10 9 8 7 6 5 4 3 2 1 0
OTG Interrupt Enable Rise register: bit description Symbol OTG_SUSPEND OTG_TMR_TIMEOUT B_SE0_SRP B_SESS_END BDIS_ACON OTG_RESUME RMT_CONN ID DP_SRP A_B_SESS_VLD VBUS_VLD Description reserved IRQ asserted when the bus is idle for more than 3 ms IRQ asserted on OTG timer timeout IRQ asserted when at least 2 ms of SE0 is detected in the B-idle state IRQ asserted when VBUS is less than 0.8 V IRQ asserted on BDIS_ACON condition IRQ asserted on J-K resume IRQ asserted on RMT_CONN IRQ asserted on the ID pin transition from LOW to HIGH IRQ asserted when DP is asserted during SRP IRQ asserted on the A-session valid for the A-device or on the B-session valid for the B-device IRQ asserted on the rising edge of VBUS
9.5.4 OTG Timer register
9.5.4.1 OTG Timer register (Low word S/C: 0388h/038Ah; high word S/C: 038Ch/038Eh) This is a 32-bit register organized as two 16-bit fields. These two fields have separate set and clear addresses. Table 90 shows the bit allocation of the register.
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Table 90: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access
[1]
OTG Timer register: bit allocation 31 START_ TMR 0 R/S/C 23 0 R/S/C 15 0 R/S/C 7 0 R/S/C 0 R/S/C 22 0 R/S/C 14 0 R/S/C 6 0 R/S/C 0 R/S/C 21 0 R/S/C 13 0 R/S/C 5 0 R/S/C 0 R/S/C 20 0 R/S/C 12 0 R/S/C 4 0 R/S/C 30 29 28 27 reserved [1] 0 R/S/C 19 0 R/S/C 11 0 R/S/C 3 0 R/S/C 0 R/S/C 18 0 R/S/C 10 0 R/S/C 2 0 R/S/C 0 R/S/C 17 0 R/S/C 9 0 R/S/C 1 0 R/S/C 0 R/S/C 16 0 R/S/C 8 0 R/S/C 0 0 R/S/C 26 25 24
TIMER_INIT_VALUE[23:16]
TIMER_INIT_VALUE[15:8]
TIMER_INIT_VALUE[7:0]
The reserved bits should always be written with the reset value.
Table 91: Bit 31
OTG Timer register: bit description Symbol START_ TMR Description This is the start/stop bit of the OTG timer. Writing logic 1 will cause the OTG timer to load TMR_INIT_VALUE into the counter and start to count. Writing logic 0 will stop the timer. This bit is automatically cleared when the OTG timer is timed out. 0 -- stop the timer 1 -- start the timer.
30 to 24 23 to 0
TIMER_INIT_ VALUE[23:0]
reserved These bits define the initial value used by the OTG timer. The timer interval is 0.01 ms. Maximum time allowed is 167.772 s.
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10. Peripheral Controller
10.1 Introduction
The design of the Peripheral Controller in the ISP1761 is compatible with the Philips ISP1582 Hi-Speed Universal Serial Bus peripheral controller IC. The functionality of the Peripheral Controller in the ISP1761 is similar to the ISP1582 in the 16-bit bus mode. In addition, the register sets are also similar, with only a few variations. The USB Chapter 9 protocol handling and data transfer operations of the Peripheral Controller are executed using external firmware. The external microcontroller or microprocessor can access the Peripheral Controller-specific registers through the local bus interface. The transfer of data between a microprocessor and the Peripheral Controller can be done in the PIO mode or the programmed DMA mode. For details on general functional description of the Peripheral Controller, refer to the ISP1582 data sheet. For details on the software programming, refer to ISP1581 Programming Guide (AN10004) and ISP1582/83 Control Pipe (AN10031).
10.1.1 Direct Memory Access (DMA)
The DMA controller of the ISP1761 is used to transfer data between the system memory and endpoints buffers. It is a slave DMA controller that requires an external DMA master to control the transfer. 10.1.1.1 DMA for the IN endpoint When the internal DMA is enabled and at least one buffer is free, the DC_DREQ line is asserted. The external DMA controller then starts negotiating for control of the bus. As soon as it has access, it asserts the DC_DACK line and starts writing data. The burst length is programmable. When the number of bytes equal to the burst length has been written, the DC_DREQ line is deasserted. As a result, the DMA controller deasserts the DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next burst. When the buffer is full, the DC_DREQ line is deasserted and the buffer is validated (which means that it is sent to the host at the next IN token). When the DMA transfer is terminated, the buffer is also validated (even if it is not full). 10.1.1.2 DMA for the OUT endpoint When the internal DMA is enabled and at least one buffer is full, the DC_DREQ line is asserted. The external DMA controller then starts negotiating for control of the bus. As soon as it has access, it asserts the DC_DACK line and starts reading data. The burst length is programmable. When the number of bytes equal to the burst length has been read, the DC_DREQ line is deasserted. As a result, the DMA controller deasserts the DC_DACK line and releases the bus. At that moment, the whole cycle restarts for the next burst. When all the data is read, the DC_DREQ line is deasserted and the buffer is cleared (this means that it can be overwritten when a new packet arrives). 10.1.1.3 DMA initialization To reduce the power consumption, a controllable clock that drives the DMA controller circuits is turned off, by default. If the DMA functionality is required by an application, DMACLKON (bit 9) of the Mode register (address: 020Ch) must be enabled during
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initialization of the Peripheral Controller. If DMA is not required by the application, DMACLKON can be permanently disabled to save current. The burst counter, DMA bus width, and the polarity of DC_DREQ and DC_DACK must be accordingly set. The ISP1761 supports only the counter mode DMA transfer. To enable the counter mode, ensure that DIS_XFER_CNT in the DcDMAConfiguration register (address: 0238h) is set to zero. Set bit EOT_POL in the DMA Hardware register (address: 023Ch) to logic 1, to make the EOT function invalid because the ISP1761 does not support the external EOT mode. Before starting the DMA transfer, preset the interrupt enable bit IEDMA in the Interrupt Enable register (address: 0214h) and the DMA Interrupt Enable register (address: 0254h). The ISP1761 supports two interrupt trigger modes: level and edge. The pulse width, which in an edge mode, is determined by setting the Interrupt Pulse Width register (address: 0280h). The default value is 1Eh, which indicates that the interrupt pulse width is 1 s. The minimum interrupt pulse width is approximately 30 ns when set to logic 1. Do not write a zero to this register. The interrupt polarity also must be correctly set. Remark: DMA can apply to all endpoints on the chip. It, however, can only take place for one endpoint at a time. The selected endpoint is assigned by setting the endpoint number in the DMA Endpoint register (address: 0258h). It will also internally redirect the endpoint buffer of the selected endpoint to the DMA controller bus. In addition, it requires a preceding process to program the endpoint type, the endpoint maximum packet size, and the direction of the endpoint. When setting the Endpoint Index register (address: 022Ch), the endpoint buffer of the selected endpoint is directed to the internal CPU bus for the PIO access. Therefore, it is required to reconfigure the Endpoint Index register with endpoint number, which is not an endpoint number in use for the DMA transfer to avoid any confusion. 10.1.1.4 Starting DMA Dynamically assign the DMA Transfer Counter register (address: 0234h) for each DMA transfer. The transfer will end once transfer counter reaches zero. Bit DMA_XFER_OK in the DMA Interrupt Reason register (address: 0250h) will be asserted to indicate that the DMA transfer has successfully stopped. If the transfer counter is larger than the burst counter, the DC_DREQ signal will drop at the end of each burst transfer. DC_DREQ will reassert at the beginning of each burst. For a 32-bit DMA transfer, the minimum burst length is 4 B. This means that the burst length is only one DMA cycle. Therefore, DC_DREQ and DC_DACK will toggle by each DMA cycle. For a 16-bit DMA transfer, the minimum burst length is 2 B. Setting bit GDMA read or GDMA write in the DMA Command register (address: 0230h) will start the DMA transfer. 10.1.1.5 DMA stop and interrupt handling The DMA transfer will either successfully complete or terminate, which can be identified by reading the status in the DcInterrupt register (address: 0218h) and DMA Interrupt Reason register (address: 0250h) while in the Interrupt Service Routine.
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If bit DMA_XFER_OK in the DMA Interrupt Reason register is asserted, it means that the transfer counter has reached zero and the DMA transfer is successfully stopped. If bit INT_EOT in the DMA Interrupt Reason register is set, it indicates that a short or empty packet is received. This means that DMA transfer terminated. Normally, for an OUT transfer, it means that remote host wishes to terminate the DMA transfer. If both the bits DMA_XFER_OK and INT_EOT are set, it means that the transfer counter reached zero and the last packet of the transfer is a short packet. Therefore, the DMA transfer is successfully stopped. Setting bit GDMA Stop in the DMA Command register (address: 0230h) will force the DMA to stop and bit GDMA_STOP in the DMA Interrupt Reason register (address: 0250h) will be set to indicate this event. Setting bit Reset DMA in the DMA Command register (address: 0230h) will force the DMA to stop and initialize the DMA core to its power-on state.
10.2 Endpoint description
Each USB peripheral is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the USB host and the USB peripheral. At design time, each endpoint is assigned a unique endpoint identifier; see Table 92. The combination of the peripheral address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced. The peripheral controller has 8 kB of internal FIFO memory, which is shared among the enabled USB endpoints. The two control endpoints are fixed 64 B long. Any of the 7 IN and 7 OUT endpoints can be separately enabled or disabled. The endpoint type (interrupt, isochronous or bulk) and packet size of these endpoints can be individually configured, depending on the requirements of the application. Optional double buffering increases the data throughput of these data endpoints.
Table 92: Endpoint identifier EP0RX EP0TX EP1RX EP1TX EP2RX EP2TX EP3RX EP3TX EP4RX EP4TX EP5RX EP5TX EP6RX
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Endpoint access and programmability Maximum packet size 64 B (fixed) 64 B (fixed) Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Double buffering Endpoint type No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Control IN Control OUT Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Programmable Direction IN OUT IN OUT IN OUT IN OUT IN OUT IN OUT IN
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Endpoint access and programmability...continued Maximum packet size Programmable Programmable Programmable Double buffering Endpoint type Yes Yes Yes Programmable Programmable Programmable Direction OUT IN OUT
Table 92: Endpoint identifier EP6TX EP7RX EP7TX
10.3 Differences between the ISP1761 and ISP1582 Peripheral Controller
This section explains the variations between the ISP1761 and ISP1582 Peripheral Controller in terms of register bits and their associated functions.
10.3.1 ISP1761 initialization registers
* The ISP1582 supports the 16-bit bus access. The register addresses are 2 B aligned.
The ISP1761 supports the 16-bit and 32-bits bus accesses. To support the 32-bit access, the DATA_BUS_WIDTH bit in the HW Mode Control register must be initialized.
* In 32-bit bus access mode, the register addresses are 4 B aligned. Therefore, the
DcBufferStatus register can be accessed using the upper-two bytes of the Buffer Length register.
* The SOFTCT bit in the Mode register has been removed. The DP_PULLUP control bit
in the OTG Control register is used in the ISP1761 in place of the SOFTCT bit in the ISP1582.
* Added the Interrupt Pulse Width register to define the pulse width of the interrupt
signal.
10.3.2 ISP1761 DMA
* * * *
The DACK-only mode has been removed. It only supports the counter mode. The external-EOT mode has been removed. There is no EOT pin on the chip. Supports the 16-bit and 32-bit DMA. Does not support the 8-bit DMA. The RD_N and WR_N signals are available for the DMA data strobe. These signals are also used as data strobe signals during the PIO access. An internal multiplex will redirect these signals to the DMA controller for the DMA transfer or to registers for the PIO access.
For details on the DMA programming, refer to application note ISP1761 Peripheral DMA Initialization (AN10040).
10.3.3 ISP1761 peripheral suspend indication
* A HIGH level indicates that the peripheral has entered suspend mode. The pulse
indication mode has been removed.
10.3.4 ISP1761 interrupt and DMA common mode
In the common mode, the interrupt and DMA signals of the Peripheral Controller are redirected to pins that are used by the Host Controller because the Host Controller and the Peripheral Controller share the same pins. Some control bits must be set in the HW Mode Control register, see Section 8.3.1.
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10.4 Peripheral Controller-specific registers
Table 93: Address 0200h 020Ch 0210h 0212h 0214h 0300h 0374h 022Ch 0228h 0220h 021Ch 021Eh 0204h 0208h 0230h 0234h 0238h 023Ch 0250h 0254h 0258h 0264h 0218h 0270h 0274h 0278h 027Ch 0280h 0284h Peripheral Controller-specific register overview Register Address Mode Interrupt Configuration Debug DcInterruptEnable HW Mode Control OTG Control Endpoint Index Control Function Data Port Buffer Length DcBufferStatus Endpoint MaxPacketSize Endpoint Type DMA Command DMA Transfer Counter DcDMAConfiguration DMA Hardware DMA Interrupt Reason DMA Interrupt Enable DMA Endpoint DMA Burst Counter DcInterrupt DcChipID Frame Number DcScratch Unlock Device Interrupt Pulse Width Test Mode Reset value 00h 0000h FCh 0000h 0000 0000h 0000 0000h 0000 0086h 00h 00h 0000h 0000h 00h 0000h 0000h FFh 0000 0000h 0001h 04h 0000h 0000h 00h 0002h 0000 0000h 0015 8210h 0000h 0000h 0000h 001Eh 00h References Section 10.4.1 on page 102 Section 10.4.2 on page 103 Section 10.4.3 on page 104 Section 10.4.4 on page 105 Section 10.4.5 on page 106 Section 8.3.1 on page 42 Section 9.5.2.1 on page 92 Section 10.5.1 on page 107 Section 10.5.2 on page 109 Section 10.5.3 on page 109 Section 10.5.4 on page 110 Section 10.5.5 on page 111 Section 10.5.6 on page 111 Section 10.5.7 on page 113 Section 10.6.1 on page 114 Section 10.6.2 on page 115 Section 10.6.3 on page 116 Section 10.6.4 on page 117 Section 10.6.5 on page 118 Section 10.6.6 on page 119 Section 10.6.7 on page 120 Section 10.6.8 on page 120 Section 10.7.1 on page 121 Section 10.7.2 on page 123 Section 10.7.3 on page 123 Section 10.7.4 on page 124 Section 10.7.5 on page 124 Section 10.7.6 on page 125 Section 10.7.7 on page 125
Initialization registers
Data flow registers
DMA registers
General registers
10.4.1 Address register (R/W: 0200h)
This register sets the USB assigned address and enables the USB peripheral. Table 94 shows the bit allocation of the register. The DEVADDR bits will be cleared whenever a bus reset, a power-on reset or a soft reset occurs. The DEVEN bit will be cleared whenever a power-on reset or a soft reset occurs, and will be set after a bus reset.
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In response to the standard USB request SET_ADDRESS, the firmware must write the (enabled) peripheral address to the Address register, followed by sending an empty packet to the host. The new peripheral address is activated when the peripheral receives acknowledgment from the host.
Table 94: Bit Symbol Reset Bus reset Access Address register: bit allocation 7 DEVEN 0 1 R/W 0 0 R/W 0 0 R/W 0 0 R/W 6 5 4 3 DEVADDR[6:0] 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 2 1 0
Table 95: Bit 7 6 to 0
Address register: bit description Symbol DEVEN DEVADDR[6:0] Description Device Enable: Logic 1 enables the peripheral. Device Address: This field specifies the USB device peripheral.
10.4.2 Mode register (R/W: 020Ch)
This register consists of 2 B (bit allocation: see Table 96). The Mode register controls resume, suspend and wake-up behavior, interrupt activity, soft reset and clock signals.
Table 96: Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
Mode register: bit allocation 15 14 13 reserved [1] 0 0 R/W 7 CLKAON 0 0 R/W 0 0 R/W 6 SNDRSU 0 0 R/W 0 0 R/W 5 GOSUSP 0 0 R/W 0 0 R/W 4 SFRESET 0 0 R/W 0 0 R/W 3 GLINTENA 0 unchanged R/W 0 0 R/W 2 WKUPCS 0 0 R/W 0 0 R/W 12 11 10 9 DMACLK ON 0 0 R/W 1 reserved [1] 0 unchanged R/W 8 VBUSSTAT 0 0 R/W 0
The reserved bits should always be written with the reset value.
Table 97: Bit 15 to 10 9
Mode register: bit description Symbol DMACLKON Description reserved DMA Clock On: 1 -- Supply clock to the DMA circuit 0 -- Power saving mode. The DMA circuit will stop completely to save power.
8
VBUSSTAT
VBUS Status: This bit reflects the VBUS pin status.
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Mode register: bit description...continued Symbol CLKAON Description Clock Always On: 1 -- Enable the Clock-Always-On feature 0 -- Disable the Clock-Always-On feature. When the Clock-Always-On feature is disabled, a GOSUSP event can stop the clock. (The clock is stopped after a delay of approximately 2 ms). Therefore, the Peripheral Controller will consume less power. If the Clock-Always-On feature is enabled, the clocks are always running and the GOSUSP event is unable to stop the clock while the Peripheral Controller enters the suspend state.
Table 97: Bit 7
6 5 4
SNDRSU GOSUSP SFRESET
Send Resume: Writing logic 1, followed by logic 0 will generate an upstream resume signal of 10 ms duration, after a 5 ms delay. Go Suspend: Writing logic 1, followed by logic 0 will activate suspend mode. Soft Reset: Writing logic 1, followed by logic 0 will enable a software-initiated reset to the ISP1761. A soft reset is similar to a hardware-initiated reset (using the RESET_N pin). Global Interrupt Enable: Logic 1 enables all interrupts. Individual interrupts can be masked by clearing the corresponding bits in the DcInterruptEnable register. When this bit is not set, an unmasked interrupt will not generate an interrupt trigger on the interrupt pin. If the global interrupt, however, is enabled while there is any pending unmasked interrupt, an interrupt signal will be immediately generated on the interrupt pin. (If the interrupt is set to the pulse mode, the interrupt events that were generated before the global interrupt is enabled may be dropped.)
3
GLINTENA
2
WKUPCS
Wake up on Chip Select: Logic 1 enables wake up through a valid register read on the ISP1761. (A read will invoke the chip clock to restart. A write to the register before the clock is stable may cause malfunctioning.) reserved
1 to 0
-
10.4.3 Interrupt Configuration register (R/W: 0210h)
This 1 B register determines the behavior and polarity of the INT output. The bit allocation is shown in Table 98. When the USB SIE receives or generates an ACK, NAK or STALL, it will generate interrupts depending on three Debug mode fields. CDBGMOD[1:0] -- Interrupts for the control endpoint 0 DDBGMODIN[1:0] -- Interrupts for the DATA IN endpoints 1 to 7 DDBGMODOUT[1:0] -- Interrupts for the DATA OUT endpoints 1 to 7. The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow you to individually configure when the ISP1761 sends an interrupt to the external microprocessor. Table 100 lists the available combinations. Bit INTPOL controls the signal polarity of the INT output: active HIGH or LOW, rising or falling edge. For level-triggering, bit INTLVL must be made logic 0. By setting INTLVL to logic 1, an interrupt will generate a pulse of 60 ns (edge-triggering).
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Table 98: Bit Symbol Reset Bus reset Access
Interrupt Configuration register: bit allocation 7 1 1 R/W 6 1 1 R/W Table 99: Bit 7 to 6 5 to 4 3 to 2 1 5 1 1 R/W 4 1 1 R/W 3 1 1 R/W 2 1 1 R/W 1 INTLVL 0 unchanged R/W 0 INTPOL 0 unchanged R/W CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0]
Interrupt Configuration register: bit description Symbol CDBGMOD[1:0] DDBGMODIN[1:0] DDBGMODOUT[1:0] INTLVL Description Control 0 Debug Mode: For values, see Table 100 Data Debug Mode IN: For values, see Table 100 Data Debug Mode OUT: For values, see Table 100 Interrupt Level: Selects the signaling mode on output INT (0 = level; 1 = pulsed). In the pulsed mode, an interrupt produces a 60 ns pulse. Bus reset value: unchanged. Interrupt Polarity: Selects signal polarity on output INT (0 = active LOW; 1 = active HIGH). Bus reset value: unchanged.
0
INTPOL
Table 100: Debug mode settings Value 00h 01h 1Xh
[1]
CDBGMOD interrupt on all ACK and NAK interrupt on all ACK interrupt on all ACK and first NAK [1]
DDBGMODIN interrupt on all ACK and NAK interrupt on ACK interrupt on all ACK and first NAK [1]
DDBGMODOUT interrupt on all ACK, NYET and NAK interrupt on ACK and NYET interrupt on all ACK, NYET and first NAK [1]
First NAK: The first NAK on an IN or OUT token after a previous ACK response.
10.4.4 Debug register (R/W: 0212h)
This register can be accessed using address 0212h in 16-bit bus access mode or using the upper-two bytes of the Interrupt Configuration register in 32-bit bus access mode. For the bit allocation, see Table 101.
Table 101: Debug register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
15 0 0 R/W 7 0 0 R/W
14 0 0 R/W 6 0 0 R/W
13 0 0 R/W 5 0 0 R/W
12 reserved [1] 0 0 R/W 4 reserved [1] 0 0 R/W
11 0 0 R/W 3 0 0 R/W
10 0 0 R/W 2 0 0 R/W
9 0 0 R/W 1 0 0 R/W
8 0 0 R/W 0 DEBUG 0 0 R/W
The reserved bits should always be written with the reset value.
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Table 102: Debug register: bit allocation Bit 15 to 1 0 Symbol DEBUG Description reserved Always set this bit to logic 0 when the ISP1761 is in 16-bit bus access mode, or set bit 16 of the Interrupt Configuration register to logic 0 when the ISP1761 is in 32-bit bus access mode.
10.4.5 DcInterruptEnable register (R/W: 0214h)
This register enables or disables individual interrupt sources. The interrupt for each endpoint can be individually controlled through the associated IEPnRX or IEPnTX bits, here n represents the endpoint number. All interrupts can be globally disabled through bit GLINTENA in the Mode register (see Table 96). An interrupt is generated when the USB SIE receives or generates an ACK or NAK on the USB bus. The interrupt generation depends on the Debug mode settings of bit fields CDBGMOD[1:0], DDBGMODIN[1:0] and DDBGMODOUT[1:0]. All data IN transactions use the Transmit buffers (TX) that are handled by the DDBGMODIN bits. All data OUT transactions go through the Receive buffers (RX) that are handled by the DDBGMODOUT bits. Transactions on control endpoint 0--IN, OUT and SETUP--are handled by the CDBGMOD bits. Interrupts caused by events on the USB bus (SOF, Pseudo SOF, suspend, resume, bus reset, setup and high-speed status) can also be individually controlled. A bus reset disables all enabled interrupts except bit IEBRST (bus reset), which remains unchanged. The DcInterruptEnable register consists of 4 B. The bit allocation is given in Table 103.
Table 103: DcInterruptEnable register: bit allocation Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access 0 0 R/W 23 IEP6TX 0 0 R/W 15 IEP2TX 0 0 R/W 0 0 R/W 22 IEP6RX 0 0 R/W 14 IEP2RX 0 0 R/W 0 0 R/W 21 IEP5TX 0 0 R/W 13 IEP1TX 0 0 R/W 31 30 29 28 reserved [1] 0 0 R/W 20 IEP5RX 0 0 R/W 12 IEP1RX 0 0 R/W 0 0 R/W 19 IEP4TX 0 0 R/W 11 IEP0TX 0 0 R/W 0 0 R/W 18 IEP4RX 0 0 R/W 10 IEP0RX 0 0 R/W 27 26 25 IEP7TX 0 0 R/W 17 IEP3TX 0 0 R/W 9 reserved
[1]
24 IEP7RX 0 0 R/W 16 IEP3RX 0 0 R/W 8 IEP0SETUP 0 0 R/W
0 0 R/W
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6 5 IEHS_STA 0 0 R/W 4 IERESM 0 0 R/W 3 IESUSP 0 0 R/W 2 IEPSOF 0 0 R/W 1 IESOF 0 0 R/W 0 IEBRST 0 unchanged R/W
Bit Symbol Reset Bus Reset Access
[1]
7 IEVBUS 0 0 R/W
IEDMA 0 0 R/W
The reserved bits should always be written with the reset value.
Table 104: DcInterruptEnable register: bit description Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX EP2TX EP2RX EP1TX IEP1RX IEP0TX IEP0RX IEP0SETUP IEVBUS IEDMA IEHS_STA IERESM IESUSP IEPSOF IESOF IEBRST Description reserved Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the indicated endpoint. Logic 1 enables interrupt from the control IN endpoint 0. Logic 1 enables interrupt from the control OUT endpoint 0. reserved Logic 1 enables interrupt for the setup data received on endpoint 0. Logic 1 enables interrupt for VBUS sensing. Logic 1 enables interrupt on detection of a DMA status change. Logic 1 enables interrupt on detection of a high-speed status change. Logic 1 enables interrupt on detection of a resume state. Logic 1 enables interrupt on detection of a suspend state. Logic 1 enables interrupt on detection of a Pseudo SOF. Logic 1 enables interrupt on detection of an SOF. Logic 1 enables interrupt on detection of a bus reset.
10.5 Data flow registers
10.5.1 Endpoint Index register (R/W: 022Ch)
The Endpoint Index register selects a target endpoint for register access by the microcontroller. The register consists of 1 B, and the bit allocation is shown in Table 105.
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The following registers are indexed:
* * * * * *
Buffer Length DcBufferStatus Control Function Data Port Endpoint MaxPacketSize Endpoint Type.
For example, to access the OUT data buffer of endpoint 1 using the Data Port register, the Endpoint Index register must be written first with 02h. Remark: The Endpoint Index register and the DMA Endpoint Index register must not point to the same endpoint.
Table 105: Endpoint Index register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7 reserved [1] 0 0 R/W
6 0 0 R/W
5 EP0SETUP 0 0 R/W
4 0 0 R/W
3 0 0 R/W
2 0 0 R/W
1 0 0 R/W
0 DIR 0 0 R/W
ENDPIDX[3:0]
The reserved bits should always be written with the reset value.
Table 106: Endpoint Index register: bit description Bit 7 to 6 5 Symbol EP0SETUP Description reserved Endpoint 0 Setup: Selects the SETUP buffer for endpoint 0. 0 -- EP0 data buffer 1 -- SETUP buffer. Must be logic 0 for access to endpoints other than endpoint 0. 4 to 1 0 ENDPIDX[3:0] Endpoint Index: Selects the target endpoint for register access of Buffer Length, Control Function, Data Port, Endpoint Type and MaxPacketSize. DIR Direction bit: Sets the target endpoint as IN or OUT. 0 -- Target endpoint refers to OUT (RX) FIFO 1 -- Target endpoint refers to IN (TX) FIFO. Table 107: Addressing of endpoint 0 buffers Buffer name SETUP Data OUT Data IN EP0SETUP 1 0 0 ENDPIDX 00h 00h 00h DIR 0 0 1
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10.5.2 Control Function register (R/W: 0228h)
The Control Function register performs the buffer management on endpoints. It consists of 1 B, and the bit configuration is given in Table 108. The register bits can stall, clear or validate any enabled data endpoint. Before accessing this register, the Endpoint Index register must be written first to specify the target endpoint.
Table 108: Control Function register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7 0 0 R/W
6 reserved [1] 0 0 R/W
5 0 0 R/W
4 CLBUF 0 0 R/W
3 VENDP 0 0 R/W
2 DSEN 0 0 R/W
1 STATUS 0 0 R/W
0 STALL 0 0 R/W
The reserved bits should always be written with the reset value.
Table 109: Control Function register: bit description Bit 4 Symbol CLBUF Description reserved Clear Buffer: Logic 1 clears the RX buffer of the indexed endpoint; the TX buffer is not affected. The RX buffer is automatically cleared once the endpoint is completely read. This bit is set only when it is necessary to forcefully clear the buffer. Validate Endpoint: Logic 1 validates the data in the TX FIFO of an IN endpoint for sending on the next IN token. In general, the endpoint is automatically validated when its FIFO byte count has reached the endpoint MaxPacketSize. This bit is set only when it is necessary to validate the endpoint with the FIFO byte count that is below the Endpoint MaxPacketSize. Data Stage Enable: This bit controls the response of the ISP1761 to a control transfer. When this bit is set, the ISP1761 goes to the data stage; otherwise, the ISP1761 will NAK the data stage transfer until the firmware explicitly responds to the setup command. Status Acknowledge: Only applicable for control IN and OUT. This bit controls the generation of ACK or NAK during the status stage of a SETUP transfer. It is automatically cleared when the status stage is completed and a SETUP token is received. No interrupt signal will be generated. 0 -- Sends NAK 1 -- Sends an empty packet following the IN token (host-to-peripheral) or ACK following the OUT token (peripheral-to-host). 0 STALL Stall Endpoint: Logic 1 stalls the indexed endpoint. This bit is not applicable for isochronous transfers. Remark: `Stall'ing a data endpoint will confuse the Data Toggle bit regarding the stalled endpoint because the internal logic starts from where it is stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0 or logic 1 in the Endpoint Type register) to reset the PID. 7 to 5 -
3
VENDP
2
DSEN
1
STATUS
10.5.3 Data Port register (R/W: 0220h)
This 2 B register provides direct access for a microcontroller to the FIFO of the indexed endpoint. The bit description is shown in Table 110.
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Peripheral to host (IN endpoint): After each write, an internal counter is automatically incremented by two to the next location in the TX FIFO. When all bytes have been written (FIFO byte count = endpoint MaxPacketSize), the buffer is automatically validated. The data packet will then be sent on the next IN token. Whenever required, the Control Function register (bit VENDP) can validate the endpoint whose byte count is less than MaxPacketSize. Host to peripheral (OUT endpoint): After each read, an internal counter is automatically decremented by two to the next location in the RX FIFO. When all bytes have been read, the buffer contents are automatically cleared. A new data packet can then be received on the next OUT token. The buffer contents can also be cleared through the Control Function register (bit CLBUF), whenever it is necessary to forcefully clear the contents. Remark: The buffer can be automatically validated or cleared using the Buffer Length register.
Table 110: Data Port register: bit description Bit Symbol Access Value R/W 0000h Description Data Port: A 500 ns delay may be required for the first read from the Data Port. 15 to 0 DATAPORT[15:0]
10.5.4 Buffer Length register (R/W: 021Ch)
This register determines the current packet size (DATACOUNT) of the indexed endpoint FIFO. The bit description is given in Table 111. The Buffer Length register is automatically loaded with the FIFO size, when the Endpoint MaxPacketSize register is written (see Table 115). A smaller value can be written when required. After a bus reset, the Buffer Length register is made zero. IN endpoint: When the data transfer is performed in multiples of MaxPacketSize, the Buffer Length register is not significant. This register is useful only when transferring data that is not a multiple of MaxPacketSize. The following two examples demonstrate the significance of the Buffer Length register. Example 1: Consider that the transfer size is 512 B and the MaxPacketSize is programmed as 64 B, the Buffer Length register need not be filled. This is because the transfer size is a multiple of MaxPacketSize, and the MaxPacketSize packets will be automatically validated because the last packet is also of MaxPacketSize. Example 2: Consider that the transfer size is 510 B and the MaxPacketSize is programmed as 64 B, the Buffer Length register should be filled with 62 B just before the microcontroller writes the last packet of 62 B. This ensures that the last packet, which is a short packet of 62 B, is automatically validated. Use the VENDP bit in the Control register if you are not using the Buffer Length register. This is applicable only to the PIO mode access. OUT endpoint: The DATACOUNT value is automatically initialized to the number of data bytes sent by the host on each ACK. Remark: When using a 16-bit microprocessor bus, the last byte of an odd-sized packet is output as the lower byte (LSByte).
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Table 111: Buffer Length register: bit description Bit Symbol Access Value R/W 0000h Description Data Count: Determines the current packet size of the indexed endpoint FIFO. 15 to 0 DATACOUNT[15:0]
10.5.5 DcBufferStatus register (R/W: 021Eh)
This register is accessed using an index. The endpoint index must first be set before accessing this register for the corresponding endpoint. It reflects the status of the endpoint FIFO. Table 112 shows the bit allocation of the DcBufferStatus register.
Table 112: DcBufferStatus register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7 0 0 R/W
6 0 0 R/W
5 reserved [1] 0 0 R/W
4 0 0 R/W
3 0 0 R/W
2 0 0 R/W
1 BUF1 0 0 R/W
0 BUF0 0 0 R/W
The reserved bits should always be written with the reset value.
Table 113: DcBufferStatus register: bit description Bit 7 to 2 1 to 0 Symbol BUF[1:0] Description reserved Buffer: 00 -- The buffers are not filled. 01 -- One of the buffers is filled. 10 -- One of the buffers is filled. 11 -- Both the buffers are filled.
10.5.6 Endpoint MaxPacketSize register (R/W: 0204h)
This register determines the maximum packet size for all endpoints, except control 0. The register contains 2 B, and the bit allocation is given in Table 114. Each time the register is written, the Buffer Length registers of all endpoints are reinitialized to the FFOSZ field value. The NTRANS bits control the number of transactions allowed in a single microframe (for high-speed isochronous and interrupt endpoints only).
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Table 114: Endpoint MaxPacketSize register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
15 0 0 R/W 7 0 0 R/W
14 reserved [1] 0 0 R/W 6 0 0 R/W
13 0 0 R/W 5 0 0 R/W
12 0 0 R/W 4
11 0 0 R/W 3
10 0 0 R/W 2 0 0 R/W
9 FFOSZ[10:8] 0 0 R/W 1 0 0 R/W
8 0 0 R/W 0 0 0 R/W
NTRANS[1:0]
FFOSZ[7:0] 0 0 R/W 0 0 R/W
The reserved bits should always be written with the reset value.
Table 115: Endpoint MaxPacketSize register: bit description Bit 15 to 13 12 to 11 Symbol NTRANS[1:0] Description reserved Number of Transactions. HS mode only. 00 -- 1 packet per microframe 01 -- 2 packets per microframe 10 -- 3 packets per microframe 11 -- reserved. These bits are applicable only for isochronous or interrupt transactions. 10 to 0 FFOSZ[10:0] FIFO Size: Sets the FIFO size, in bytes, for the indexed endpoint. Applies to both high-speed and full-speed operations (see Table 116).
Table 116: Programmable FIFO size NTRANS[1:0] 0h 0h 0h 0h 0h 0h 0h 2h FFOSZ[10:0] 08h 10h 20h 40h 80h 100h 200h 400h Non-isochronous 8B 16 B 32 B 64 B 128 B 256 B 512 B Isochronous 3072 B
Each programmable FIFO can be independently configured through its Endpoint MaxPacketSize register (R/W: 04h), but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 8192 B.
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10.5.7 Endpoint Type register (R/W: 0208h)
This register sets the endpoint type of the indexed endpoint: isochronous, bulk or interrupt. It also serves to enable the endpoint and configure it for double buffering. Automatic generation of an empty packet for a zero-length TX buffer can be disabled using bit NOEMPKT. The register contains 2 B, and the bit allocation is shown in Table 117.
Table 117: Endpoint Type register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
15 0 0 7 0 0 R/W
14 0 0 6 reserved [1] 0 0 R/W
13 0 0 5 0 0 R/W
12 reserved [1] 0 0 4 NOEMPKT 0 0 R/W
11 0 0 3 ENABLE 0 0 R/W
10 0 0 2 DBLBUF 0 0 R/W
9 0 0 1 0 0 R/W
8 0 0 0 0 0 R/W
ENDPTYP[1:0]
The reserved bits should always be written with the reset value.
Table 118: Endpoint Type register: bit description Bit 15 to 5 4 Symbol NOEMPKT Description reserved No Empty Packet: Logic 0 causes an empty packet to be appended to the next IN token of the USB data, if the Buffer Length register or the Endpoint MaxPacketSize register is zero. Logic 1 disables this function. This bit is applicable only in the DMA mode. Endpoint Enable: Logic 1 enables the FIFO of the indexed endpoint. The memory size is allocated as specified in the Endpoint MaxPacketSize register. Logic 0 disables the FIFO. Remark: `Stall'ing a data endpoint will confuse the Data Toggle bit on the stalled endpoint because the internal logic starts from where it has stalled. Therefore, the Data Toggle bit must be reset by disabling and re-enabling the corresponding endpoint (by setting bit ENABLE to logic 0 or logic 1 in the Endpoint Type register) to reset the PID. 2 1 to 0 DBLBUF Double Buffering: Logic 1 enables double buffering for the indexed endpoint. Logic 0 disables double buffering. 00 -- not used 01 -- Isochronous 10 -- Bulk 11 -- Interrupt.
3
ENABLE
ENDPTYP[1:0] Endpoint Type: These bits select the endpoint type as follows.
10.6 DMA registers
The Generic DMA (GDMA) transfer can be done by writing the proper opcode in the DMA Command register. The control bits are given in Table 119. GDMA read or write (opcode = 00h/01h) for the Generic DMA slave mode
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The GDMA (slave) can operate in the counter mode. RD_N and WR_N are DMA data strobe signals. These signals are also used as data strobe signals during the PIO access. An internal multiplex will redirect these signals to the DMA Controller for the DMA transfer or to registers for the PIO access. In the counter mode, the DIS_XFER_CNT bit in the DcDMAConfiguration register must be set to logic 0. The DMA Transfer Counter register must be programmed before any DMA command is issued. The DMA transfer counter is set by writing from the LSByte to the MSByte (address: 234h to 237h). The DMA transfer count is internally updated only after the MSByte is written. Once the DMA transfer is started, the transfer counter starts decrementing and on reaching 0, the DMA_XFER_OK bit is set and an interrupt is generated by the ISP1761. The DMA transfer starts once the DMA command is issued. Any of the following three ways will terminate this DMA transfer:
* Detecting an internal EOT (short packet on an OUT token) * Resetting the DMA * GDMA stop command.
There are two interrupts that are programmable to differentiate the method of DMA termination: the INT_EOT and DMA_XFER_OK bits in the DMA Interrupt Reason register. For details, see Table 131.
Table 119: Control bits for GDMA read or write (opcode = 00h/01h) Control bits Mode register DMACLKON MODE[1:0] WIDTH Set DMACLKON to logic 1 Determines the active read or write data strobe signals Selects the DMA bus width: 16 or 32 bits Table 97 Table 126 DcDMAConfiguration register Description Reference
DIS_XFER_CNT Disables the use of the DMA Transfer Counter DMA Hardware register ENDIAN[1:0] DACK_POL, DREQ_POL Determines whether the data is to be byte swapped or normal Select the polarity of the DMA handshake signals Table 128
Remark: The DMA bus defaults to three-state, until a DMA command is executed. All the other control signals are not three-state.
10.6.1 DMA Command register (W: 0230h)
The DMA Command register is a 1 B register (for bit allocation, see Table 120) that initiates all DMA transfer activities on the DMA controller. The register is write-only: reading it will return FFh. Remark: The DMA bus will be in three-state until a DMA command is executed.
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Table 120: DMA Command register: bit allocation Bit Symbol Reset Bus reset Access 1 1 W 1 1 W 1 1 W 7 6 5 4 1 1 W 3 1 1 W 2 1 1 W 1 1 1 W 0 1 1 W DMA_CMD[7:0]
Table 121: DMA Command register: bit description Bit 7 to 0 Symbol DMA_CMD[7:0] Description DMA command code; see Table 122.
Table 122: DMA commands Code 00h 01h Name GDMA Read GDMA Write Description Generic DMA IN token transfer (slave mode only): Data is transferred from the external DMA bus to the internal buffer. Generic DMA OUT token transfer (slave mode only): Data is transferred from the internal buffer to the external DMA bus. reserved Validate Buffer (for debugging only): Request from the microcontroller to validate the endpoint buffer, following a DMA to USB data transfer. Clear Buffer: Request from the microcontroller to clear the endpoint buffer after a USB to DMA data transfer. reserved Reset DMA: Initializes the DMA core to its power-on reset state. Remark: When the DMA core is reset during the Reset DMA command, the DREQ, DACK, RD_N and WR_N handshake pins will be temporarily asserted. This can confuse the external DMA controller. To prevent this, start the external DMA controller only after the DMA reset. 12h 13h GDMA Stop reserved GDMA stop: This command stops the GDMA data transfer. Any data in the OUT endpoint that is not transferred by the DMA will remain in the buffer. The FIFO data for the IN endpoint will be written to the endpoint buffer. An interrupt bit will be set to indicate that the DMA Stop command is complete. reserved
02h to 0Dh 0Eh Validate Buffer
0Fh 10h 11h
Clear Buffer Reset DMA
14h to FFh -
10.6.2 DMA Transfer Counter register (R/W: 0234h)
This 4 B register sets up the total byte count for a DMA transfer (DMACR). It indicates the remaining number of bytes left for transfer. The bit allocation is given in Table 123. For IN endpoint -- As there is a FIFO in the ISP1761 DMA controller, some data may remain in the FIFO during the DMA transfer. The maximum FIFO size is 8 B, and the maximum delay time for the data to be shifted to endpoint buffer is 60 ns. For OUT endpoint -- Data will not be cleared for the endpoint buffer until all the data has been read from the DMA FIFO.
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If the DMA counter is disabled in the DMA transfer, it will still decrement and rollover when it reaches zero.
Table 123: DMA Transfer Counter register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 0 0 R/W 0 0 R/W 0 0 R/W 7 0 0 R/W 6 0 0 R/W 5 0 0 R/W 15 0 0 R/W 14 0 0 R/W 13 0 0 R/W 23 0 0 R/W 22 0 0 R/W 21 31 30 29 28 0 0 R/W 20 0 0 R/W 12 0 0 R/W 4 0 0 R/W 27 0 0 R/W 19 0 0 R/W 11 0 0 R/W 3 0 0 R/W 26 0 0 R/W 18 0 0 R/W 10 0 0 R/W 2 0 0 R/W 25 0 0 R/W 17 0 0 R/W 9 0 0 R/W 1 0 0 R/W 24 0 0 R/W 16 0 0 R/W 8 0 0 R/W 0 0 0 R/W DMACR4 = DMACR[31:24]
DMACR3 = DMACR[23:16]
DMACR2 = DMACR[15:8]
DMACR1 = DMACR[7:0]
Table 124: DMA Transfer Counter register: bit description Bit 31 to 24 23 to 16 15 to 8 7 to 0 Symbol DMACR4, DMACR[31:24] DMACR3, DMACR[23:16] DMACR2, DMACR[15:8] DMACR1, DMACR[7:0] Description DMA Counter 4: DMA transfer counter byte 4 (MSB) DMA Counter 3: DMA transfer counter byte 3 DMA Counter 2: DMA transfer counter byte 2 DMA Counter 1: DMA transfer counter byte 1 (LSB)
10.6.3 DcDMAConfiguration register (R/W: 0238h)
This register defines the DMA configuration for the GDMA mode. The DcDMAConfiguration register consists of 2 B. The bit allocation is given in Table 125.
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Table 125: DcDMAConfiguration register: bit allocation Bit Symbol Reset Bus Reset Access Bit Symbol Reset Bus Reset Access
[1]
15 0 0 R/W 7 DIS_ XFER_CNT 0 0 R/W
14 0 0 R/W 6
13 0 0 R/W 5 reserved [1]
12 reserved [1] 0 0 R/W 4
11 0 0 R/W 3 MODE[1:0]
10 0 0 R/W 2
9 0 0 R/W 1 reserved
8 0 0 R/W 0 WIDTH 1 1 R/W
0 0 R/W
0 0 R/W
0 0 R/W
0 0 R/W
0 0 R/W
0 0 R/W
The reserved bits should always be written with the reset value.
Table 126: DcDMAConfiguration register: bit description Bit 15 to 8 7 6 to 4 3 to 2 Symbol DIS_XFER_CNT MODE[1:0] Description reserved Disable Transfer Counter: Logic 1 disables the DMA Transfer Counter (see Table 123). reserved Mode: These bits only affect the GDMA slave handshake signals. 00 -- WR_N slave strobes data from the DMA bus into the ISP1761; RD_N slave puts data from the ISP1761 on the DMA bus 01, 10, 11 -- reserved 1 0 WIDTH reserved Width: This bit selects the DMA bus width for the GDMA slave. 0 -- 32-bit data bus 1 -- 16-bit data bus.
10.6.4 DMA Hardware register (R/W: 023Ch)
The DMA Hardware register consists of 1 B. The bit allocation is shown in Table 127. This register determines the polarity of the bus control signals (DACK and DREQ). It also controls whether the upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]) for the GDMA (slave) mode.
Table 127: DMA Hardware register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7
6
5 EOT_POL 0 0 R/W
4 reserved [1] 0 0 R/W
3 DACK_ POL 0 0 R/W
2 DREQ_ POL 1 1 R/W
1 reserved [1] 0 0 R/W
0
ENDIAN[1:0] 0 0 R/W 0 0 R/W
0 0 R/W
The reserved bits should always be written with the reset value.
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Table 128: DMA Hardware register: bit description Bit 7 to 6 Symbol ENDIAN[1:0] Description Endian: These bits determine whether the data bus is swapped between the internal RAM and the DMA bus. 00 -- Normal data representation 16-bit bus: MSB on DATA[15:8], LSB on DATA[7:0] 01 -- Swapped data representation 16-bit bus: MSB on DATA[7:0], LSB on DATA[15:8] 10, 11 -- reserved. 5 EOT_POL Selects the polarity of the End-Of-Transfer input; used in GDMA (slave) mode only. 0 -- EOT is active LOW 1 -- EOT is active HIGH. 4 3 DACK_POL reserved DACK Polarity: Selects the DMA acknowledgment polarity. 0 -- DACK is active LOW 1 -- DACK is active HIGH. 2 DREQ_POL DREQ Polarity: Selects the DMA request polarity. 0 -- DREQ is active LOW 1 -- DREQ is active HIGH. 1 to 0 reserved
10.6.5 DMA Interrupt Reason register (R/W: 0250h)
This 2 B register shows the source(s) of DMA interrupt. Each bit is refreshed after a DMA command is executed. An interrupt source is cleared by writing logic 1 to the corresponding bit. When the register is read, perform a logical AND with the corresponding bits of the DMA Interrupt Enable register. The bit allocation is given in Table 129.
Table 129: DMA Interrupt Reason register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
15
14 reserved
13
12 GDMA_ STOP
11 reserved 0 0 R/W 3 reserved [1] 0 0 R/W
10 INT_EOT 0 0 R/W 2 0 0 R/W
9 reserved [1] 0 0 R/W 1 0 0 R/W
8 DMA_ XFER_OK 0 0 R/W 0 0 0 R/W
0 0 R/W 7 0 0 R/W
0 0 R/W 6 0 0 R/W
0 0 R/W 5 0 0 R/W
0 0 R/W 4 0 0 R/W
The reserved bits should always be written with the reset value.
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Table 130: DMA Interrupt Reason register: bit description Bit 15 to 13 12 Symbol GDMA_STOP Description reserved GDMA Stop: When the GDMA_STOP command is issued to the DMA Command registers, it means that the DMA transfer has successfully terminated. reserved Internal EOT: Logic 1 indicates that an internal EOT is detected; see Table 131. reserved DMA Transfer OK: Logic 1 indicates that the DMA transfer has been completed (DMA Transfer Counter has become zero). This bit is only used in the GDMA (slave) mode. reserved
11 10 9 8
INT_EOT DMA_XFER_OK
7 to 0
-
Table 131: Internal EOT-functional relation with the DMA_XFER_OK bit INT_EOT 1 1 0 DMA_XFER_OK 0 1 1 Description During the DMA transfer, there is a premature termination with short packet. DMA transfer is completed with short packet and the DMA transfer counter has reached 0. DMA transfer is completed without any short packet and the DMA transfer counter has reached 0.
10.6.6 DMA Interrupt Enable register (R/W: 0254h)
This 2 B register controls the interrupt generation of the source bits in the DMA Interrupt Reason register. The bit allocation is given in Table 132. The bit description is given in Table 130. Logic 1 enables the interrupt generation. The values after a (bus) reset are logic 0 (disabled).
Table 132: DMA Interrupt Enable register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
15
14 reserved [1]
13
12 IE_GDMA_ STOP
11 reserved [1] 0 0 R/W 3 reserved [1] 0 0 R/W
10 IE_INT_ EOT 0 0 R/W 2 0 0 R/W
9 reserved [1] 0 0 R/W 1 0 0 R/W
8 IE_DMA_ XFER_OK 0 0 R/W 0 0 0 R/W
0 0 R/W 7 0 0 R/W
0 0 R/W 6 0 0 R/W
0 0 R/W 5 0 0 R/W
0 0 R/W 4 0 0 R/W
The reserved bits should always be written with the reset value.
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10.6.7 DMA Endpoint register (R/W: 0258h)
This 1 B register selects a USB endpoint FIFO as the source or destination for DMA transfers. The bit allocation is given in Table 133.
Table 133: DMA Endpoint register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7 0 0 R/W
6 reserved [1] 0 0 R/W
5 0 0 R/W
4 0 0 R/W
3 0 0 R/W
2 EPIDX[2:0] 0 0 R/W
1 0 0 R/W
0 DMADIR 0 0 R/W
The reserved bits should always be written with the reset value.
Table 134: DMA Endpoint register: bit description Bit 7 to 4 3 to 1 0 Symbol EPIDX[2:0] DMADIR Description reserved Selects the indicated endpoint for DMA access DMA Direction: 0 -- Selects the RX/OUT FIFO for DMA read transfers 1 -- Selects the TX/IN FIFO for DMA write transfers.
The DMA Endpoint register must not reference the endpoint that is indexed by the Endpoint Index register (022Ch) at any time. Doing so would result in data corruption. Therefore, if the DMA Endpoint register is unused, point it to an unused endpoint. If the DMA Endpoint register, however, is pointed to an active endpoint, the firmware must not reference the same endpoint on the Endpoint Index register.
10.6.8 DMA Burst Counter register (R/W: 0264h)
The bit allocation of the register is given in Table 135.
Table 135: DMA Burst Counter register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access
[1]
15 0 0 R/W 7 0 0 R/W
14 reserved [1] 0 0 R/W 6 0 0 R/W
13 0 0 R/W 5 0 0 R/W
12 0 0 R/W 4 0 0 R/W
11 0 0 R/W 3 0 0 R/W
10 BURSTCOUNTER[12:8] 0 0 R/W 2 0 0 R/W
9 0 0 R/W 1 1 1 R/W
8 0 0 R/W 0 0 0 R/W
BURSTCOUNTER[7:0]
The reserved bits should always be written with the reset value.
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Table 136: DMA Burst Counter register: bit description Bit 15 to 13 12 to 0 Symbol BURST COUNTER [12:0] Description reserved Burst Counter: This register defines the burst length. The counter must be programmed to be a multiple of two in the 16-bit mode and four in the 32-bit mode. The value of the burst counter should be programmed so that the buffer counter is a factor of the burst counter. In the 16-bit mode, DREQ will drop at every DMA read or write cycle when the burst counter equals 2. In the 32-bit mode, DREQ will drop at every DMA read or write cycle when the burst counter equals 4.
10.7 General registers
10.7.1 DcInterrupt register (R/W: 0218h)
The DcInterrupt register consists of 4 B. The bit allocation is given in Table 137. When a bit is set in the DcInterrupt register, it indicates that the hardware condition for an interrupt has occurred. When the DcInterrupt register content is nonzero, the INT output will be asserted. On detecting the interrupt, the external microprocessor must read the DcInterrupt register to determine the source of the interrupt. Each endpoint buffer has a dedicated interrupt bit (EPnTX, EPnRX). In addition, various bus states can generate an interrupt: resume, suspend, pseudo SOF, SOF and bus reset. The DMA controller has only one interrupt bit: the source for a DMA interrupt is shown in the DMA Interrupt Reason register. Each interrupt bit can be individually cleared by writing logic 1. The DMA Interrupt bit can be cleared by writing logic 1 to the related interrupt source bit in the DMA Interrupt Reason register and writing logic 1 to the DMA bit of the DcInterrupt register.
Table 137: DcInterrupt register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access 0 0 R/W 23 EP6TX 0 0 R/W 15 EP2TX 0 0 R/W 0 0 R/W 22 EP6RX 0 0 R/W 14 EP2RX 0 0 R/W 0 0 R/W 21 EP5TX 0 0 R/W 13 EP1TX 0 0 R/W 31 30 29 reserved [1] 0 0 R/W 20 EP5RX 0 0 R/W 12 EP1RX 0 0 R/W 0 0 R/W 19 EP4TX 0 0 R/W 11 EP0TX 0 0 R/W 0 0 R/W 18 EP4RX 0 0 R/W 10 EP0RX 0 0 R/W 28 27 26 25 EP7TX 0 0 R/W 17 EP3TX 0 0 R/W 9 reserved [1] 0 0 R/W 24 EP7RX 0 0 R/W 16 EP3RX 0 0 R/W 8 EP0SETUP 0 0 R/W
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5 HS_STAT 0 0 R/W 4 RESUME 0 0 R/W 3 SUSP 0 0 R/W 2 PSOF 0 0 R/W 1 SOF 0 0 R/W 0 BRESET 0 unchanged R/W
Bit Symbol Reset Bus reset Access
[1]
7 VBUS 0 0 R/W
6 DMA 0 0 R/W
The reserved bits should always be written with the reset value.
Table 138: DcInterrupt register: bit description Bit 31 to 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 Symbol EP7TX EP7RX EP6TX EP6RX EP5TX EP5RX EP4TX EP4RX EP3TX EP3RX EP2TX EP2RX EP1TX EP1RX EP0TX EP0RX EP0SETUP VBUS DMA HS_STAT Description reserved Logic 1 indicates the endpoint 7 TX buffer as interrupt source. Logic 1 indicates the endpoint 7 RX buffer as interrupt source. Logic 1 indicates the endpoint 6 TX buffer as interrupt source. Logic 1 indicates the endpoint 6 RX buffer as interrupt source. Logic 1 indicates the endpoint 5 TX buffer as interrupt source. Logic 1 indicates the endpoint 5 RX buffer as interrupt source. Logic 1 indicates the endpoint 4 TX buffer as interrupt source. Logic 1 indicates the endpoint 4 RX buffer as interrupt source. Logic 1 indicates the endpoint 3 TX buffer as interrupt source. Logic 1 indicates the endpoint 3 RX buffer as interrupt source. Logic 1 indicates the endpoint 2 TX buffer as interrupt source. Logic 1 indicates the endpoint 2 RX buffer as interrupt source. Logic 1 indicates the endpoint 1 TX buffer as interrupt source. Logic 1 indicates the endpoint 1 RX buffer as interrupt source. Logic 1 indicates the endpoint 0 data TX buffer as interrupt source. Logic 1 indicates the endpoint 0 data RX buffer as interrupt source. reserved Logic 1 indicates that a SETUP token was received on endpoint 0. Logic 1 indicates VBUS is turned on. DMA status: Logic 1 indicates a change in the DMA Status register. High Speed Status: Logic 1 indicates a change from the full-speed to high-speed mode (HS connection). This bit is not set, when the system goes into the full-speed suspend. Resume status: Logic 1 indicates that a status change from suspend to resume (active) was detected. Suspend status: Logic 1 indicates that a status change from active to suspend was detected on the bus.
4 3
RESUME SUSP
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Table 138: DcInterrupt register: bit description...continued Bit 2 Symbol PSOF Description Pseudo SOF interrupt: Logic 1 indicates that a pseudo SOF or SOF was received. Pseudo SOF is an internally generated clock signal (full-speed: 1 ms period, high-speed: 125 s period) synchronized to the USB bus SOF or SOF. SOF interrupt: Logic 1 indicates that a SOF or SOF was received. Bus Reset: Logic 1 indicates that a USB bus reset was detected. When the SW_SEL_HC_DC bit in the OTG Control register is set, BRESET will not be set, instead, this interrupt bit will report SE0 on DP and DM for 2 ms.
1 0
SOF BRESET
10.7.2 DcChipID register (R: 0270h)
This read-only register contains the chip identification and the hardware version numbers. The firmware should check this information to determine the functions and features supported. The register contains 3 B, and the bit allocation is shown in Table 139.
Table 139: DcChipID register: bit description Bit Symbol Access Value R 0015 8210h Description Chip ID: This registers represents the hardware version number (0015h) and the chip ID (8210h) for the Peripheral Controller. 31 to 0 CHIPID [31:0]
10.7.3 Frame Number register (R: 0274h)
This read-only register contains the frame number of the last successfully received Start-Of-Frame (SOF). The register contains 2 B, and the bit allocation is given in Table 140. In the case of 8-bit access, the register content is returned lower byte first.
Table 140: Frame Number register: bit allocation Bit Symbol Power Reset Bus Reset Access Bit Symbol Power Reset Bus Reset Access 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 7 15 reserved 0 0 R 6 0 0 R 5 14 13 12 MICROSOF[2:0] 0 0 R 4 SOFR[7:0] 0 0 R 0 0 R 0 0 R 0 0 R 0 0 R 3 0 0 R 2 11 10 9 SOFR[10:8] 0 0 R 1 0 0 R 0 8
Table 141: Frame Number register: bit description Bit 15 to 14 13 to 11 10 to 0 Symbol MICROSOF[2:0] SOFR[10:0] Description reserved microframe number frame number
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10.7.4 DcScratch register (R/W: 0278h)
This 16-bit register can be used by the firmware to save and restore information. For example, the peripheral status before it enters the suspend state. The content of this register will not be altered by a bus reset. The bit allocation is given in Table 142.
Table 142: DcScratch register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access R/W R/W R/W 0 0 0 0 unchanged R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 4 SFIRL[7:0] 0 0 0 0 0 0 0 0 unchanged R/W R/W 3 R/W 2 R/W 1 R/W 0 15 14 13 12 SFIRH[7:0] 0 0 0 0 11 10 9 8
Table 143: DcScratch register: bit description Bit 15 to 8 7 to 0 Symbol SFIRH[7:0] SFIRL[7:0] Description Scratch firmware information register (higher byte) Scratch firmware information register (lower byte)
10.7.5 Unlock Device register (W: 027Ch)
To protect the registers from getting corrupted when the ISP1761 goes into suspend, the write operation is disabled if the PWRON bit in the Mode register is set to logic 0. In this case, when the chip resumes, the Unlock Device command must be first issued to this register before attempting to write to the rest of the registers. This is done by writing unlock code (AA37h) to this register. The bit allocation of the Unlock Device register is given in Table 144.
Table 144: Unlock Device register: bit allocation Bit Symbol Reset Bus reset Access Bit Symbol Reset Bus reset Access W W W W 7 W 6 W 5 15 14 13 12 11 10 9 8 ULCODE[15:8] = AAh not applicable not applicable W 4 W 3 W 2 W 1 W 0
ULCODE[7:0] = 37h not applicable not applicable W W W W W
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Table 145: Unlock Device register: bit description Bit 15 to 0 Symbol ULCODE[15:0] Description Unlock Code: Writing data AA37h unlocks the internal registers and FIFOs for writing, following a resume.
When the PWRON bit in the Mode register is logic 1, the chip is powered. In such a case, you do not need to issue the Unlock command because the microprocessor is powered and therefore, the RD_N, WR_N and CS_N signals maintain their states. When the PWRON bit is logic 0, the RD_N, WR_N and CS_N signals are floating because the microprocessor is not powered. To protect the ISP1761 registers from being corrupted during suspend, register write is locked when the chip goes into suspend. Therefore, you need to issue the Unlock command to unlock the ISP1761 registers.
10.7.6 Interrupt Pulse Width register (R/W: 0280h)
Table 146 shows the bit description of the register.
Table 146: Interrupt Pulse Width register: bit description Bit Symbol Access Value 001Eh Description Interrupt Pulse Width: The interrupt signal pulse width is configurable while it is in the pulse signaling mode. The minimum pulse width is 3.33 ns when this register is set to logic 1. The power-on reset value of 1Eh allows a pulse of 1 s to be generated. 15 to 0 INTR_PULSE R/W _WIDTH[15:0
10.7.7 Test Mode register (R/W: 0284h)
This 1 B register allows the firmware to set the DP and DM pins to predetermined states for testing purposes. The bit allocation is given in Table 147. Remark: Only one bit can be set to logic 1 at a time.
Table 147: Test Mode register: bit allocation Bit Symbol Reset Bus reset Access
[1]
7 FORCEHS 0 0 R/W
6 reserved [1] 0 0 R/W
5 0 0 R/W
4 FORCEFS 0 0 R/W
3 PRBS 0 0 R/W
2 KSTATE 0 0 R/W
1 JSTATE 0 0 R/W
0 SE0_NAK 0 0 R/W
The reserved bits should always be written with the reset value.
Table 148: Test Mode register: bit description Bit 7 6 to 5 4 3 Symbol FORCEHS FORCEFS PRBS Description Force High-Speed: Logic 1 [1] forces the hardware to the high-speed mode only and disables the chirp detection logic. reserved. Force Full-Speed: Logic 1 [1] forces the physical layer to the full-speed mode only and disables the chirp detection logic. Logic 1 [2] sets the DP and DM pins to toggle in a predetermined random pattern.
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Table 148: Test Mode register: bit description...continued Bit 2 1 0 Symbol KSTATE JSTATE SE0_NAK Description K State: Writing logic 1 [2] sets the DP and DM pins to the K state. J State: Writing logic 1 [2] sets the DP and DM pins to the J state. SE0 NAK: Writing logic 1 [2] sets the DP and DM pins to a high-speed quiescent state. The device only responds to a valid high-speed IN token with a NAK.
[1] [2]
Either FORCEHS or FORCEFS should be set at a time. Of the four bits (PRBS, KSTATE, JSTATE and SE0_NAK), only one bit should be set at a time.
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11. Power consumption
Table 149: Power consumption Number of ports working One port working (high-speed) VCC = 5.0 V, VCC(I/O) = 3.3 V VCC = 3.3 V, VCC(I/O) = 3.3 V VCC = 5.0 V, VCC(I/O) = 1.8 V VCC = 3.3 V, VCC(I/O) = 1.8 V Two ports working (high-speed) VCC = 5.0 V, VCC(I/O) = 3.3 V VCC = 3.3 V, VCC(I/O) = 3.3 V VCC = 5.0 V, VCC(I/O) = 1.8 V VCC = 3.3 V, VCC(I/O) = 1.8 V Three ports working (high-speed) VCC = 5.0 V, VCC(I/O) = 3.3 V VCC = 3.3 V, VCC(I/O) = 3.3 V VCC = 5.0 V, VCC(I/O) = 1.8 V VCC = 3.3 V, VCC(I/O) = 1.8 V 130 mA 117 mA 122 mA 117 mA 110 mA 97 mA 102 mA 97 mA 90 mA 77 mA 82 mA 77 mA ICC
Remark: The idle operating current (ICC), that is, when the ISP1761 is in operational mode--initialized and without any devices connected, is 70 mA. The additional current consumption on ICC is below 1 mA per port in the case of full-speed and low-speed devices. Remark: Deep-sleep suspend mode ensures the lowest power consumption when VCC is always supplied to the ISP1761. In this case, the suspend current (ICC(susp)) is typically about 150 A at room temperature. The suspend current may increase if the ambient temperature increases. For details, see Section 7.6. Remark: In hybrid mode, when VCC is disconnected ICC(I/O) will be generally below 100 A. The average value is 60 A to 70 A.
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12. Limiting values
Table 150: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC(I/O) VCC(5V0) VCC(C_IN) Ilu Vesd Tstg Parameter supply voltage supply voltage supply voltage latch-up current electrostatic discharge voltage storage temperature VI < 0 or VI > VCC ILI < 1 A Conditions Min -0.5 -0.5 -4000 -40 Max +4.6 +5.6 4.5 100 +4000 +125 Unit V V V mA V C
13. Recommended operating conditions
Table 151: Recommended operating conditions Symbol VCC(I/O) VCC(5V0) VCC(C_IN) Tamb ICC(susp) Parameter supply voltage supply voltage supply voltage ambient temperature deep sleep suspend current Tamb = 25 C, VCC(5V0) = 3.3 V
[1]
Conditions VCC(I/O) = 3.3 V VCC(I/O) = 1.8 V
Min 3.0 1.65 3 3.15 -40 -
Typ 3.3 1.8 150
Max 3.6 1.95 5.5 4.2 +85 -
Unit V V V V C A
[1]
For details, see Figure 17 and Figure 18.
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14. Static characteristics
Table 152: Static characteristics: digital pins All digital pins [1], except pins ID, PSW1_N, PSW2_N, PSW3_N and VBAT_ON_N. VCC(I/O) = 3.0 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH VIL Vhys VOL VOH ILI CIN
[1]
Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage input leakage current input pin capacitance
Conditions
Min 2.0 0.4
Typ 2.75
Max 0.8 0.7 0.4 1 -
Unit V V V V V A pF
IOL = 3 mA 0 < VIN < VCC(I/O)
2.4 -
Includes OC1_N/VBUS, OC2_N and OC3_N when used as digital overcurrent pins.
Table 153: Static characteristics: digital pins All digital pins [1], except pins ID, PSW1_N, PSW2_N, PSW3_N and VBAT_ON_N. VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH VIL Vhys VOL VOH ILI CIN
[1]
Parameter HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage HIGH-level output voltage input leakage current input pin capacitance
Conditions
Min 1.2 0.4
Typ 2.75
Max 0.5 0.7 0.22VCC(I/O) 1 -
Unit V V V V V A pF
IOL = 3 mA 0 < VIN < VCC(I/O)
-
0.8VCC(I/O) -
Includes OC1_N/VBUS, OC2_N and OC3_N when used as digital overcurrent pins.
Table 154: Static characteristics: PSW1_N, PSW2_N, PSW3_N VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VOL VOH Parameter LOW-level output voltage HIGH-level output voltage Conditions IOL = 8 mA, pull-up to VCC(5V0) pull-up to VCC(I/O) Min Typ VCC(I/O) Max 0.4 Unit V V
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Table 155: Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VHSSQ Parameter squelch detection threshold (differential signal amplitude) disconnect detection threshold (differential signal amplitude) Conditions squelch detected no squelch detected disconnect detected disconnect not detected VHSCM data signaling common mode voltage range idle state data signaling HIGH data signaling LOW Chirp J level (differential voltage) Chirp K level (differential voltage) HIGH-level input voltage (drive) HIGH-level input voltage (floating) LOW-level input voltage differential input sensitivity differential common mode range HIGH-level output voltage LOW-level output voltage SEI output signal crossover point voltage |VDP - VDM| Min 150 625 -50 Typ Max 100 525 +500 Unit mV mV mV mV mV Input levels for high-speed
VHSDSC
Output levels for high-speed VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK VIH VIHZ VIL VDI VCM VOH VOL VOSEI VCRS
[1]
-10 360 -10 700 [1] -900 [1] 2.0 2.7 0.2 0.8 2.8 0 0.8 1.3
-
+10 440 +10 1100 -500 3.6 0.8 2.5 3.6 0.3 2.0
mV mV mV mV mV V V V V V V V V V
Input levels for full-speed and low-speed
Output levels for full-speed and low-speed
The HS termination resistor is disabled, and the pull-up resistor is connected. Only during reset, when both the hub and the device are capable of the high-speed operation.
Table 156: Static characteristics: REF5V VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol VIH Parameter HIGH-level input voltage Conditions Min Typ 5 Max Unit V
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150 ICP (mA)
004aaa667
Tamb = -40 C 25 C 100 C 100
50
0 3 3.4 3.8 4.2 VCC(C_IN) (V)
Fig 17. Charge pump current versus voltage at various temperatures (worst case)
150 ICP (mA)
004aaa668
Tamb = -40 C 25 C 100 C 100
50
0 3 3.4 3.8 VCC(C_IN) (V) 4.2
Fig 18. Charge pump current versus voltage at various temperatures (typical case)
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15. Dynamic characteristics
Table 157: Dynamic characteristics: system clock timing Symbol fclk Parameter clock frequency [1] Conditions crystal [2] oscillator External clock input J Vclk tCR, tCF
[1] [2]
Min -
Typ 12 12 50 VCC(I/O) -
Max 500 3
Unit MHz MHz ps % V ns
Crystal oscillator
external clock jitter clock duty cycle amplitude rise time and fall time
Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator used depends on VCC(I/O). Recommended values for external capacitors when using a crystal are 22 pF to 27 pF.
Table 158: Dynamic characteristics: CPU interface block VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol SR Parameter output slew rate (rise, fall) Conditions standard load Min 1 Typ Max 4 Unit V/ns
Table 159: Dynamic characteristics: high-speed source electrical characteristics VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tHSR tHSF ZHSDRV Parameter high-speed differential rise time drive output resistance (this also serves as a high-speed termination) data rate microframe interval consecutive microframe interval difference Conditions 10 % to 90 % Min 500 500 40.5 Typ 45 Max 49.5 Unit ps ps Driver characteristics
high-speed differential fall time 90 % to 10 % includes the RS resistor
Clock timing tHSDRAT tHSFRAM tHSRFI 479.76 124.9375 1 480.24 125.0625 four high-speed bit times Mbit/s s ns
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Table 160: Dynamic characteristics: full-speed source electrical characteristics VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tFR Parameter rise time Conditions CL = 50 pF; 10 % to 90 % of |VOH - VOL| CL = 50 pF; 90 % to 10 % of |VOH - VOL| Min 4 Typ Max 20 Unit ns Driver characteristics
tFF
fall time
4
-
20
ns
tFRFM ZDRV
differential rise and fall time matching driver output resistance for the driver that is not high-speed capable source jitter for differential transition to SEO transition source SE0 interval of EOP receiver SE0 interval of EOP source jitter for differential transition to SEO transition source SE0 interval of EOP receiver SE0 interval of EOP width of SE0 interval during differential transaction low-speed timing full-speed timing
90 28
-
111.1 44
%
Data timing: see Figure 19 tFDEOP tFEOPT tFEOPR tLDEOP tLEOPT tLEOPR tFST -2 160 82 -40 1.25 670 +5 175 +100 1.5 14 ns ns ns ns s ns ns
Table 161: Dynamic characteristics: low-speed source electrical characteristics VCC(I/O) = 1.65 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tLR tLF tLRFM Parameter rise time fall time differential rise and fall time matching Conditions Min 75 75 90 Typ Max 300 300 125 Unit ns ns % Driver characteristics
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TPERIOD +3.3 V crossover point differential data lines crossover point extended
0V differential data to SE0/EOP skew N x TPERIOD + t DEOP source EOP width: t EOPT receiver EOP width: t EOPR
mgr776
TPERIOD is the bit duration corresponding with the USB data rate. tDEOP is the source jitter for differential transition to SE0 transition. Full-speed timing symbols have a subscript prefix `F', low-speed timing symbols have a prefix `L'.
Fig 19. USB source differential data-to-EOP transition skew and EOP width
15.1 Host timing
15.1.1 PIO timing
15.1.1.1 Register or memory write
th31 A[17:1] address 01 tsu21 CS_N tsu31 WR_N tsu11 DATA data 01 Tcy11 data 02
004aaa527
address 02 th21
tw11 th11
Fig 20. Register or memory write Table 162: Register or memory write VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol th11 th21 th31 tw11 Tcy11 tsu11 tsu21 tsu31 Parameter data hold after WR_N HIGH CS_N hold after WR_N HIGH address hold after WR_N HIGH WR_N pulse width WR_N to WR_N cycle time data setup time before WR_N HIGH address setup time before WR_N HIGH CS_N setup time before WR_N HIGH Min 2 1 2 17 36 5 5 5 Max Unit ns ns ns ns ns ns ns ns
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Table 163: Register or memory write VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol th11 th21 th31 tw11 Tcy11 tsu11 tsu21 tsu31 Parameter data hold after WR_N HIGH CS_N hold after WR_N HIGH address hold after WR_N HIGH WR_N pulse width WR_N to WR_N cycle time data setup time before WR_N HIGH address setup time before WR_N HIGH CS_N setup time before WR_N HIGH Min 2 1 2 17 36 5 5 5 Max Unit ns ns ns ns ns ns ns ns
15.1.1.2
Register read
tsu12 A[17:1] tsu22 CS_N td22 tw12 RD_N Tcy12 DATA
004aaa524
address 01
address 02
td12
Fig 21. Register read Table 164: Register read VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tsu12 tsu22 tw12 td12 td22 Tcy12 Parameter address setup time before RD_N LOW CS_N setup time before RD_N LOW RD_N pulse width data valid time after RD_N LOW data valid time after RD_N HIGH read-to-read cycle time Min 0 0 td12 40 Max 35 1 Unit ns ns ns ns ns ns
Table 165: Register read VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tsu12 tsu22 tw12 Parameter address setup time before RD_N LOW CS_N setup time before RD_N LOW RD_N pulse width Min 0 0 td12 Max Unit ns ns ns
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Table 165: Register read...continued VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol td12 td22 Tcy12 Parameter data valid time after RD_N LOW data valid time after RD_N HIGH read-to-read cycle time Min 36 Max 22 1 Unit ns ns ns
15.1.1.3
Memory read
A[17:1]
address = 33C
address 1 tsu23
address 2
address 3
DATA
data
data 1
data 2
data 3
CS_N td13 WR_N tp13 td23
RD_N Tcy13 tw13
004aaa523
tsu13
Fig 22. Memory read Table 166: Memory read VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tp13 Tcy13 td13 td23 tw13 tsu13 tsu23 Parameter initial prefetch time memory RD_N cycle time data valid time after RD_N LOW data available time after RD_N HIGH RD_N pulse width CS_N setup time before RD_N LOW address setup time before RD_N LOW Min 90 40 td13 0 0 Max 31 1 Unit ns ns ns ns ns ns ns
Table 167: Memory read VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tp13 Tcy13 td13 td23
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Parameter initial prefetch time memory RD_N cycle time data valid time after RD_N LOW data available time after RD_N HIGH
Rev. 01 -- 12 January 2005
Min 90 36 -
Max 20 1
Unit ns ns ns ns
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Table 167: Memory read...continued VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tw13 tsu13 tsu23 Parameter RD_N pulse width CS_N setup time before RD_N LOW address setup time before RD_N LOW Min td13 0 0 Max Unit ns ns ns
15.1.2 DMA timing
In the following sections:
* Polarity of DACK is active HIGH * Polarity of DREQ is active HIGH.
15.1.2.1 Single cycle: DMA read
ta44 DREQ ta14 DACK tw14 RD_N ta24 DATA
004aaa530
ta34
td14
Fig 23. DMA read (single cycle) Table 168: DMA read (single cycle) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta14 ta24 td14 tw14 ta34 ta44 Parameter DACK assertion time after DREQ assertion RD_N assertion time after DACK assertion data valid time after RD_N assertion RD_N pulse width DREQ deassertion time after RD_N assertion DACK deassertion to next DREQ assertion time Min 0 0 td14 23 Max 24 56 Unit ns ns ns ns ns ns
Table 169: DMA read (single cycle) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta14 ta24 td14 Parameter DACK assertion time after DREQ assertion RD_N assertion time after DACK assertion data valid time after RD_N assertion Min 0 0 Max 20 Unit ns ns ns
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Table 169: DMA read (single cycle)...continued VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol tw14 ta34 ta44 Parameter RD_N pulse width DREQ deassertion time after RD_N assertion DACK deassertion to next DREQ assertion time Min td14 11 Max 56 Unit ns ns ns
15.1.2.2
Single cycle: DMA write
tcy15 DREQ ta15 DACK ta25 tsu15 WR_N th15 DATA data data 1
004aaa525
ta35 tw15 th25
DREQ and DACK are active HIGH.
Fig 24. DMA write (single cycle) Table 170: DMA write (single cycle) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta15 ta25 th15 th25 tsu15 ta35 tcy15 tw15 Parameter DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion data hold time after WR_N deassertion DACK hold time after WR_N deassertion data setup time before WR_N deassertion DREQ deassertion time after WR_N assertion last DACK strobe deassertion to next DREQ assertion time WR_N pulse width Min 0 1 3 0 5.5 22 82 22 Max Unit ns ns ns ns ns ns ns ns
Table 171: DMA write (single cycle) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta15 ta25 th15 th25 tsu15 Parameter DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion data hold time after WR_N deassertion DACK hold time after WR_N deassertion data setup time before WR_N deassertion Min 0 1 2 0 5.5 Max Unit ns ns ns ns ns
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Table 171: DMA write (single cycle)...continued VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta35 tcy15 tw15 Parameter DREQ deassertion time after WR_N assertion last DACK strobe deassertion to next DREQ assertion time WR_N pulse width Min 8.9 82 22 Max Unit ns ns ns
15.1.2.3
Multicycle: DMA read
ta36 DREQ ta16 DACK ta26 RD_N tw16 td16 DATA data 0 data 1 data n-1 data n Tcy16
ta46
004aaa531
DREQ and DACK are active HIGH.
Fig 25. DMA read (multicycle burst) Table 172: DMA read (multicycle burst) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta16 ta26 td16 tw16 Tcy16 ta36 ta46 Parameter DACK assertion time after DREQ assertion RD_N assertion time after DACK assertion data valid time after RD_N assertion RD_N pulse width read-to-read cycle time DACK deassertion to next DREQ assertion time Min 0 0 td16 40 Max 31 82 Unit ns ns ns ns ns ns ns
DREQ deassertion time after last burst RD_N deassertion 20
Table 173: DMA read (multicycle burst) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ta16 ta26 td16 tw16 Tcy16 ta36 ta46
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Parameter DACK assertion time after DREQ assertion RD_N assertion time after DACK assertion data valid time after RD_N assertion RD_N pulse width read-to-read cycle time DREQ deassertion time after last burst RD_N deassertion DACK deassertion to next DREQ assertion time
Rev. 01 -- 12 January 2005
Min 0 0 td16 36 11 -
Max 16 82
Unit ns ns ns ns ns ns ns
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15.1.2.4
Multicycle: DMA write
ta57 DREQ ta17 th27 DACK tsu17 Tcy17 tw17 WR_N ta27 ta47 th17 DATA data 1 data 2 data n-1 data n 004aaa526 ta37
Fig 26. DMA write (multicycle burst) Table 174: DMA write (multicycle burst) VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy17 tsu17 th17 ta17 ta27 ta37 th27 ta47 tw17 ta57 DMA write cycle time data setup time before WR_N deassertion data hold time after WR_N deassertion DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion DREQ deassertion time at last strobe (WR_N) assertion DACK hold time after WR_N deassertion strobe deassertion to next strobe assertion time WR_N pulse width DACK deassertion to next DREQ assertion time Min 51 5 2 0 2 20 0 34 17 Max 82 Unit ns ns ns ns ns ns ns ns ns ns
Table 175: DMA write (multicycle burst) VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy17 tsu17 th17 ta17 ta27 ta37 th27 ta47 tw17 ta57 DMA write cycle time data setup time before WR_N deassertion data hold time after WR_N deassertion DACK assertion time after DREQ assertion WR_N assertion time after DACK assertion DREQ deassertion time at last strobe (WR_N) assertion DACK hold time after WR_N deassertion strobe deassertion to next strobe assertion time WR_N pulse width DACK deassertion to next DREQ assertion time Min 51 5 2 0 1 0 0 34 17 Max 82 Unit ns ns ns ns ns ns ns ns ns ns
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15.2 Peripheral timing
15.2.1 PIO timing
15.2.1.1 PIO register read or write
Tcy18 td68 CS_N td48 th28 th18 AD[17:1] td18 (read) DATA[31:0] tsu18 RD_N tw18 td28 td58 td38
tsu28 (write) DATA[31:0] tsu38 WR_N tw28
th38
004aaa529
Fig 27. ISP1761 register access timing: separate address and data buses (8051 style) Table 176: PIO register read or write VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Reading tw18 tsu18 th18 td18 td28 td38 td48 Writing tw28 tsu28 th28 tsu38 th38 td58
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Min td1 0 0 33 0 0 15 0 0 5 2 1
Max 1 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
RD_N LOW pulse width address setup time before RD_N LOW address hold time after RD_N HIGH RD_N LOW to data valid delay RD_N HIGH to data outputs three-state delay RD_N HIGH to CS_N HIGH delay CS_N LOW to RD_N LOW delay WR_N LOW pulse width address setup time before WR_N LOW address hold time after WR_N HIGH data setup time before WR_N HIGH data hold time after WR_N HIGH WR_N HIGH to CS_N HIGH delay
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Table 176: PIO register read or write...continued VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter td68 General Tcy18 read or write cycle time 40 ns CS_N LOW to WR_N LOW delay Min 0 Max Unit ns
Table 177: PIO register read or write VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Reading tw18 tsu18 th18 td18 td28 td38 td48 Writing tw28 tsu28 th28 tsu38 th38 td58 td68 General Tcy18 read or write cycle time 40 ns WR_N LOW pulse width address setup time before WR_N LOW address hold time after WR_N HIGH data setup time before WR_N HIGH data hold time after WR_N HIGH WR_N HIGH to CS_N HIGH delay CS_N LOW to WR_N LOW delay 15 0 1 5 2 1 0 ns ns ns ns ns ns ns RD_N LOW pulse width address setup time before RD_N LOW address hold time after RD_N HIGH RD_N LOW to data valid delay RD_N HIGH to data outputs three-state delay RD_N HIGH to CS_N HIGH delay CS_N LOW to RD_N LOW delay td1 0 0 21 0 0 0 1 ns ns ns ns ns ns ns Min Max Unit
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15.2.2 DMA timing
15.2.2.1 DMA read or write
DREQ(2) tsu19 DACK(1) tsu39 RD_N/WR_N(1) td29 (read) DATA[31:0] tsu29 (write) DATA[31:0]
004aaa528
tw19
Tcy19
th19
td19 tw29 th29 ta19
th39
DREQ is continuously asserted until the last transfer is done or the FIFO is full. Data strobes: RD_N (read) and WR_N (write). (1) Programmable polarity: shown as active LOW. (2) Programmable polarity: shown as active HIGH.
Fig 28. DMA read or write Table 178: DMA read or write VCC(I/O) = 1.65 V to 1.95 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy19 tsu19 td19 th19 tw19 tw29 td29 th29 th39 tsu29 tsu39 ta19 read or write cycle time DREQ setup time before first DACK on DREQ on delay after last strobe off DREQ hold time after last strobe on RD_N/WR_N pulse width RD_N/WR_N recovery time read data valid delay after strobe on read data hold time after strobe off write data hold time after strobe off write data setup time before strobe off DACK setup time before RD_N/WR_N assertion DACK deassertion after RD_N/WR_N deassertion Min 75 10 33.33 0 40 36 1 10 0 0 Max 53 600 30 5 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns
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Table 179: DMA read or write VCC(I/O) = 3.3 V to 3.6 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Parameter Tcy19 tsu19 td19 th19 tw19 tw29 td29 th29 th39 tsu29 tsu39 ta19 read or write cycle time DREQ setup time before first DACK on DREQ on delay after last strobe off DREQ hold time after last strobe on RD_N/WR_N pulse width RD_N/WR_N recovery time read data valid delay after strobe on read data hold time after strobe off write data hold time after strobe off write data setup time before strobe off DACK setup time before RD_N/WR_N assertion DACK deassertion after RD_N/WR_N deassertion Min 75 10 33.33 0 39 36 1 10 0 0 Max 53 600 20 5 30 Unit ns ns ns ns ns ns ns ns ns ns ns ns
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16. Package outline
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SOT425-1
c
y X
A 102 103 65 64 ZE
e E HE A A2 A 1
(A 3) Lp L detail X
wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7o o 0
22.15 16.15 21.85 15.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-20
Fig 29. Package outline (LQFP128)
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TFBGA128: plastic thin fine-pitch ball grid array package; 128 balls; body 9 x 9 x 0.8 mm
SOT857-1
D
B
A
ball A1 index area
E
A
A2
A1 detail X
e1 e 1/2 e b v w
M M
C CAB C y1 C y
T R P N M L K J H G F E D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 11 13 15 10 12 14 16 0 DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.1 A1 0.25 0.15 A2 0.85 0.75 b 0.35 0.25 D 9.1 8.9 E 9.1 8.9 e 0.5 e1 7.5 e2 7.5 v 0.15 w 0.05 y 0.08 y1 0.1 2.5 scale 5 mm e
e2 1/2 e
X
OUTLINE VERSION SOT857-1
REFERENCES IEC JEDEC MO-195 JEITA
EUROPEAN PROJECTION
ISSUE DATE 04-05-05 04-06-22
Fig 30. Package outline (TFBGA128)
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17. Soldering
17.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
17.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept:
* below 225 C (SnPb process) or below 245 C (Pb-free process)
- for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages.
* below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a
thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high upward
pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board;
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- smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle to
the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
17.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C.
17.5 Package related soldering information
Table 180: Suitability of surface mount IC packages for wave and reflow soldering methods Package [1] BGA, HTSSON..T [3], LBGA, LFBGA, SQFP, SSOP..T [3], TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC [5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L [8], PMFP [9], WQCCN..L [8]
[1] [2]
Soldering method Wave not suitable not suitable [4] Reflow [2] suitable suitable
suitable not not recommended [5] [6] recommended [7]
suitable suitable suitable not suitable
not suitable
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible.
[3]
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Hi-Speed USB OTG controller
[4]
These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages.
[5] [6] [7] [8]
[9]
18. Abbreviations
Table 181: Abbreviations Acronym ATL DMA DSC EHCI EMI FS FIFO GPS HC HNP HS iTD ISR INT ISO ITL LS OHCI OTG PCI PDA PLL PIO PMOS POR PTD QHA QHA-SS/CS
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Description Acknowledged Transfer List Direct Memory Access Digital Still Camera Enhanced Host Controller Interface Electro-Magnetic Interference full-speed First In, First Out Global Positioning System Host Controller Host Negotiation Protocol high-speed isochronous Transfer Descriptor Interrupt Service Routine INTerrupt ISOchronous Isochronous (ISO) Transfer List low-speed Open Host Controller Interface On-the-Go Peripheral Component Interconnect Personal Digital Assistant Phase-Locked Loop Programmed Input/Output Positive-channel Metal-Oxide Semiconductor Power-On Reset Philips Transfer Descriptor Queue Head Asynchronous Queue Head Asynchronous Start Split and Complete Split
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Product data sheet
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ISP1761
Hi-Speed USB OTG controller
Table 181: Abbreviations...continued Acronym QHP RISC SiTD SIE SRP TT UHCI USB Description Queue Head Periodic Reduced Instruction Set Computer Split isochronous Transfer Descriptor Serial Interface Engine Session Request Protocol Transaction Translator Universal Host Controller Interface Universal Serial Bus
19. References
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Universal Serial Bus Specification Rev. 2.0 Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 On-The-Go Supplement to the USB Specification Rev. 1.0a Interfacing the ISP76x to the Intel(R) PXA250 Processor (AN10037) ISP1761 Peripheral DMA Initialization (AN10040) ISP176x Linux Programming Guide (AN10042) Embedded Systems Design with the ISP176x (AN10043) ISP1581 Programming Guide (AN10004) ISP1582/83 Control Pipe (AN10031).
20. Revision history
Table 182: Revision history Document ID ISP1761_1 Release date 20050112 Data sheet status Product data sheet Change notice Doc. number 9397 750 13258 Supersedes -
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ISP1761
Hi-Speed USB OTG controller
21. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
22. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
24. Trademarks
DragonBall -- is a trademark of Motorola, Inc. Hitachi -- is a registered trademark of Hitachi, Ltd. Intel -- is a registered trademark of Intel Corporation. Motorola -- is a registered trademark of Motorola, Inc. NEC -- is a registered trademark of NEC Corporation. PowerPC -- is a registered trademark of IBM Corporation. SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V. StrongARM -- is a registered trademark of ARM Limited. Toshiba -- is a registered trademark of Toshiba Corporation.
23. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
25. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
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ISP1761
Hi-Speed USB OTG controller
26. Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Table 26: Table 27: Table 28: Table 29: Table 30: Table 31: Table 32: Table 33: Table 34: Table 35: Table 36: Table 37: Table 38: Table 39: Table 40: Table 41: Table 42: Table 43: Table 44: Table 45: Table 46: Table 47: Ordering information . . . . . . . . . . . . . . . . . . . . .4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .7 Port connection scenarios . . . . . . . . . . . . . . . .16 Memory address . . . . . . . . . . . . . . . . . . . . . . .18 Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . .28 Pin status during hybrid mode . . . . . . . . . . . . .28 Host Controller-specific register overview . . . .31 CAPLENGTH register: bit description . . . . . . .32 HCIVERSION register: bit description . . . . . . .32 HCSPARAMS register: bit allocation . . . . . . . .33 HCSPARAMS register: bit description . . . . . . .33 HCCPARAMS register: bit allocation . . . . . . . .34 HCCPARAMS register: bit description . . . . . . .34 USBCMD register: bit allocation . . . . . . . . . . .35 USBCMD register: bit description . . . . . . . . . .35 USBSTS register: bit allocation . . . . . . . . . . . .36 USBSTS register: bit description . . . . . . . . . . .36 FRINDEX register: bit allocation . . . . . . . . . . .37 FRINDEX register: bit description . . . . . . . . . .37 CONFIGFLAG register: bit allocation . . . . . . .38 CONFIGFLAG register: bit description . . . . . .38 PORTSC 1 register: bit allocation . . . . . . . . . .39 PORTSC 1 register: bit description . . . . . . . . .39 ISO PTD Done Map register: bit description . .40 ISO PTD Skip Map register: bit description . . .40 ISO PTD Last PTD register: bit description . . .40 INT PTD Done Map register: bit description . .41 INT PTD Skip Map register: bit description . . .41 INT PTD Last PTD register: bit description . . .41 ATL PTD Done Map register: bit description . .42 ATL PTD Skip Map register: bit description . . .42 ATL PTD Last PTD register: bit description . . .42 HW Mode Control register: bit allocation . . . . .43 HW Mode Control register: bit description . . . .43 HcChipID register: bit description . . . . . . . . . .44 HcScratch register: bit description . . . . . . . . . .44 SW Reset register: bit allocation . . . . . . . . . . .45 SW Reset register: bit description . . . . . . . . . .45 HcDMAConfiguration register: bit allocation . .45 HcDMAConfiguration register: bit description .46 HcBufferStatus register: bit allocation . . . . . . .46 HcBufferStatus register: bit description . . . . . .47 ATL Done Timeout register: bit description . . .47 Memory register: bit allocation . . . . . . . . . . . . .48 Memory register: bit description . . . . . . . . . . .48 Edge Interrupt Count register: bit allocation . .48 Table 48: Table 49: Table 50: Table 51: Table 52: Table 53: Table 54: Table 55: Table 56: Table 57: Table 58: Table 59: Table 60: Table 61: Table 62: Table 63: Table 64: Table 65: Table 66: Table 67: Table 68: Table 69: Table 70: Table 71: Table 72: Table 73: Table 74: Table 75: Table 76: Table 77: Table 78: Table 79: Table 80: Table 81: Edge Interrupt Count register: bit description . 49 DMA Start Address register: bit allocation . . . 49 DMA Start Address register: bit description . . 50 Power Down Control register: bit allocation . . 50 Power Down Control register: bit description . 51 HcInterrupt register: bit allocation . . . . . . . . . . 52 HcInterrupt register: bit description . . . . . . . . . 53 HcInterruptEnable register: bit allocation . . . . 54 HcInterruptEnable register: bit description . . . 55 ISO IRQ MASK OR register: bit description . . 56 INT IRQ MASK OR register: bit description . . 56 ATL IRQ MASK OR register: bit description . . 56 ISO IRQ MASK AND register: bit description . 57 INT IRQ MASK AND register: bit description . 57 ATL IRQ MASK SAND register: bit description 57 High-speed bulk IN and OUT, QHA: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 High-speed bulk IN and OUT, QHA: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 High-speed isochronous IN and OUT, iTD: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 High-speed isochronous IN and OUT, iTD: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 High-speed interrupt IN and OUT, QHP: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 High-speed interrupt IN and OUT, QHP: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Start and complete split for bulk, QHASS/CS: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Start and complete split for bulk, QHASS/CS: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Start and complete split for isochronous, SiTD: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Start and complete split for isochronous, SiTD: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Start and complete split for interrupt: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Start and complete split for interrupt: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 OTG Controller-specific register overview . . . . 90 Address mapping of registers: 32-bit data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Address mapping of registers: 16-bit data bus mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Vendor ID register: bit description . . . . . . . . . . 91 Product ID register: bit description . . . . . . . . . 91 OTG Control register: bit allocation . . . . . . . . . 92 OTG Control register: bit description . . . . . . . . 92
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ISP1761
Hi-Speed USB OTG controller
Table 124:DMA Transfer Counter register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 125:DcDMAConfiguration register: bit allocation . 117 Table 126:DcDMAConfiguration register: bit description 117 Table 127:DMA Hardware register: bit allocation . . . . . . 117 Table 128:DMA Hardware register: bit description . . . . 118 Table 129:DMA Interrupt Reason register: bit allocation 118 Table 130:DMA Interrupt Reason register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 131:Internal EOT-functional relation with the DMA_XFER_OK bit . . . . . . . . . . . . . . . . . . . . 119 Table 132:DMA Interrupt Enable register: bit allocation . 119 Table 133:DMA Endpoint register: bit allocation . . . . . . 120 Table 134:DMA Endpoint register: bit description . . . . . 120 Table 135:DMA Burst Counter register: bit allocation . . 120 Table 136:DMA Burst Counter register: bit description . 121 Table 137:DcInterrupt register: bit allocation . . . . . . . . . 121 Table 138:DcInterrupt register: bit description . . . . . . . . 122 Table 139:DcChipID register: bit description . . . . . . . . . 123 Table 140:Frame Number register: bit allocation . . . . . . 123 Table 141: Frame Number register: bit description . . . . 123 Table 142:DcScratch register: bit allocation . . . . . . . . . . 124 Table 143:DcScratch register: bit description . . . . . . . . 124 Table 144:Unlock Device register: bit allocation . . . . . . 124 Table 145:Unlock Device register: bit description . . . . . 125 Table 146:Interrupt Pulse Width register: bit description 125 Table 147:Test Mode register: bit allocation . . . . . . . . . . 125 Table 148:Test Mode register: bit description . . . . . . . . 125 Table 149:Power consumption . . . . . . . . . . . . . . . . . . . . 127 Table 150:Absolute maximum ratings . . . . . . . . . . . . . . 128 Table 151:Recommended operating conditions . . . . . . . 128 Table 152:Static characteristics: digital pins . . . . . . . . . 129 Table 153:Static characteristics: digital pins . . . . . . . . . 129 Table 154:Static characteristics: PSW1_N, PSW2_N, PSW3_N . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Table 155:Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3) . . . . . . . 130 Table 156:Static characteristics: REF5V . . . . . . . . . . . . 130 Table 157:Dynamic characteristics: system clock timing 132 Table 158:Dynamic characteristics: CPU interface block 132 Table 159:Dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . . . . . . 132 Table 160:Dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . . . . . . 133 Table 161:Dynamic characteristics: low-speed source electrical characteristics . . . . . . . . . . . . . . . . 133 Table 162:Register or memory write . . . . . . . . . . . . . . . 134 Table 163:Register or memory write . . . . . . . . . . . . . . . 135 Table 164:Register read . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 165:Register read . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 166:Memory read . . . . . . . . . . . . . . . . . . . . . . . . . 136
Table 82: Table 83: Table 84: Table 85: Table 86:
OTG Status register: bit allocation . . . . . . . . . .93 OTG Status register: bit description . . . . . . . . .93 OTG Interrupt Latch register: bit allocation . . .94 OTG Interrupt Latch register: bit description . .94 OTG Interrupt Enable Fall register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Table 87: OTG Interrupt Enable Fall register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Table 88: OTG Interrupt Enable Rise register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table 89: OTG Interrupt Enable Rise register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Table 90: OTG Timer register: bit allocation . . . . . . . . . .97 Table 91: OTG Timer register: bit description . . . . . . . . .97 Table 92: Endpoint access and programmability . . . . . .100 Table 93: Peripheral Controller-specific register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Table 94: Address register: bit allocation . . . . . . . . . . .103 Table 95: Address register: bit description . . . . . . . . . .103 Table 96: Mode register: bit allocation . . . . . . . . . . . . . .103 Table 97: Mode register: bit description . . . . . . . . . . . .103 Table 98: Interrupt Configuration register: bit allocation 105 Table 99: Interrupt Configuration register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Table 100:Debug mode settings . . . . . . . . . . . . . . . . . . .105 Table 101:Debug register: bit allocation . . . . . . . . . . . . .105 Table 102:Debug register: bit allocation . . . . . . . . . . . . .106 Table 103:DcInterruptEnable register: bit allocation . . . .106 Table 104:DcInterruptEnable register: bit description . .107 Table 105:Endpoint Index register: bit allocation . . . . . .108 Table 106: Endpoint Index register: bit description . . . .108 Table 107:Addressing of endpoint 0 buffers . . . . . . . . . .108 Table 108:Control Function register: bit allocation . . . . .109 Table 109: Control Function register: bit description . . .109 Table 110:Data Port register: bit description . . . . . . . . .110 Table 111:Buffer Length register: bit description . . . . . .111 Table 112:DcBufferStatus register: bit allocation . . . . . .111 Table 113:DcBufferStatus register: bit description . . . . .111 Table 114:Endpoint MaxPacketSize register: bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Table 115: Endpoint MaxPacketSize register: bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Table 116:Programmable FIFO size . . . . . . . . . . . . . . . .112 Table 117:Endpoint Type register: bit allocation . . . . . . .113 Table 118:Endpoint Type register: bit description . . . . . .113 Table 119:Control bits for GDMA read or write (opcode = 00h/01h) . . . . . . . . . . . . . . . . . . . .114 Table 120:DMA Command register: bit allocation . . . . .115 Table 121: DMA Command register: bit description . . . .115 Table 122: DMA commands . . . . . . . . . . . . . . . . . . . . . .115 Table 123:DMA Transfer Counter register: bit allocation 116
continued >>
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ISP1761
Hi-Speed USB OTG controller
Table 167:Memory read . . . . . . . . . . . . . . . . . . . . . . . . .136 Table 168:DMA read (single cycle) . . . . . . . . . . . . . . . . .137 Table 169:DMA read (single cycle) . . . . . . . . . . . . . . . . .137 Table 170:DMA write (single cycle) . . . . . . . . . . . . . . . .138 Table 171:DMA write (single cycle) . . . . . . . . . . . . . . . .138 Table 172:DMA read (multicycle burst) . . . . . . . . . . . . .139 Table 173:DMA read (multicycle burst) . . . . . . . . . . . . .139 Table 174:DMA write (multicycle burst) . . . . . . . . . . . . .140 Table 175:DMA write (multicycle burst) . . . . . . . . . . . . .140 Table 176:PIO register read or write . . . . . . . . . . . . . . .141 Table 177:PIO register read or write . . . . . . . . . . . . . . .142 Table 178:DMA read or write . . . . . . . . . . . . . . . . . . . . .143 Table 179:DMA read or write . . . . . . . . . . . . . . . . . . . . .144 Table 180:Suitability of surface mount IC packages for wave and reflow soldering methods . . . . . . . . . . . .148 Table 181:Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .149 Table 182:Revision history . . . . . . . . . . . . . . . . . . . . . . .150
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Product data sheet
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Hi-Speed USB OTG controller
27. Figures
Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Pin configuration (LQFP128); top view. . . . . . . . . .6 Pin configuration (TFBGA128); top view. . . . . . . . .6 Internal hub. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 ISP1761 clock scheme. . . . . . . . . . . . . . . . . . . . .15 Memory segmentation and access block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 ISP1761 power supply connection. . . . . . . . . . . .27 Most commonly used power supply connection. .27 Hybrid mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Adjusting analog overcurrent detection limit (optional). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Internal power-on reset timing. . . . . . . . . . . . . . .30 Clock with respect to the external power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 NextPTD traversal rule. . . . . . . . . . . . . . . . . . . . .59 HNP sequence of events. . . . . . . . . . . . . . . . . . .86 Dual-role A-device state diagram. . . . . . . . . . . . .88 Dual-role B-device state diagram. . . . . . . . . . . . .89 Charge pump current versus voltage at various temperatures (worst case). . . . . . . . . . . . . . . . .131 Charge pump current versus voltage at various temperatures (typical case). . . . . . . . . . . . . . . .131 USB source differential data-to-EOP transition skew and EOP width. . . . . . . . . . . . . . . . . . . . . . . . . .134 Register or memory write. . . . . . . . . . . . . . . . . .134 Register read. . . . . . . . . . . . . . . . . . . . . . . . . . .135 Memory read.. . . . . . . . . . . . . . . . . . . . . . . . . . .136 DMA read (single cycle). . . . . . . . . . . . . . . . . . .137 DMA write (single cycle). . . . . . . . . . . . . . . . . . .138 DMA read (multicycle burst). . . . . . . . . . . . . . . .139 DMA write (multicycle burst). . . . . . . . . . . . . . . .140 ISP1761 register access timing: separate address and data buses (8051 style). . . . . . . . . . . . . . . .141 DMA read or write. . . . . . . . . . . . . . . . . . . . . . .143 Package outline (LQFP128). . . . . . . . . . . . . . . .145 Package outline (TFBGA128). . . . . . . . . . . . . . .146
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Product data sheet
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Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
28. Contents
1 2 3 3.1 4 5 6 6.1 6.2 7 7.1 7.1.1 7.2 7.2.1 7.2.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4 7.5 7.6 7.7 7.7.1 7.8 7.9 8 8.1 8.1.1 8.1.2 8.1.3 8.1.4 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Host/peripheral roles. . . . . . . . . . . . . . . . . . . . . 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional description . . . . . . . . . . . . . . . . . . 14 ISP1761 internal architecture: Advanced Philips Slave Host Controller and hub . . . . . . . . . . . . 14 Internal clock scheme . . . . . . . . . . . . . . . . . . . 15 Host Controller buffer memory block . . . . . . . 16 General considerations. . . . . . . . . . . . . . . . . . 16 Structure of the ISP1761 Host Controller memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Accessing the ISP1761 Host Controller memory: PIO and DMA . . . . . . . . . . . . . . . . . . . . . . . . . 19 PIO mode access--memory read cycle . . . . . 20 PIO mode access--memory write cycle. . . . . 20 PIO mode access--register read cycle . . . . . 21 PIO mode access--register write cycle . . . . . 21 DMA--read and write operations . . . . . . . . . . 21 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Phase-Locked Loop (PLL) clock multiplier . . . 24 Power management . . . . . . . . . . . . . . . . . . . . 25 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . 26 Hybrid mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Overcurrent detection . . . . . . . . . . . . . . . . . . . 29 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 30 Host Controller. . . . . . . . . . . . . . . . . . . . . . . . . 31 EHCI capability registers . . . . . . . . . . . . . . . . 32 CAPLENGTH register (R: 0000h). . . . . . . . . . 32 HCIVERSION register (R: 0002h) . . . . . . . . . 32 HCSPARAMS register (R: 0004h) . . . . . . . . . 32 HCCPARAMS register (R: 0008h) . . . . . . . . . 33 EHCI operational registers . . . . . . . . . . . . . . . 34 USBCMD register (R/W: 0020h). . . . . . . . . . . 34 USBSTS register (R/W: 0024h) . . . . . . . . . . . 35 USBINTR register (R/W: 0028h). . . . . . . . . . . 36 FRINDEX register (R/W: 002Ch) . . . . . . . . . . 36 CTRLDSSEGMENT register (R/W: 0030h) . . 37 CONFIGFLAG register (R/W: 0060h) . . . . . . . 37 PORTSC1 register (R, R/W, R/WC (field dependent): 0064h) . . . 38 8.2.8 ISO PTD Done Map register (R: 0130h) . . . . 8.2.9 ISO PTD Skip Map register (R/W: 0134h) . . . 8.2.10 ISO PTD Last PTD register (R/W: 0138h) . . . 8.2.11 INT PTD Done Map register (R: 0140h). . . . . 8.2.12 INT PTD Skip Map register (R/W: 0144h) . . . 8.2.13 INT PTD Last PTD register (R/W: 0148h) . . . 8.2.14 ATL PTD Done Map register (R: 0150h) . . . . 8.2.15 ATL PTD Skip Map register (R/W: 0154h) . . . 8.2.16 ATL PTD Last PTD register (R/W: 0158h) . . . 8.3 Configuration registers . . . . . . . . . . . . . . . . . . 8.3.1 HW Mode Control register (R/W: 0300h) . . . . 8.3.2 HcChipID register (R: 0304h). . . . . . . . . . . . . 8.3.3 HcScratch register (R/W: 0308h) . . . . . . . . . . 8.3.4 SW Reset register (R/W: 030Ch) . . . . . . . . . . 8.3.5 HcDMAConfiguration register (R/W: 0330h) . 8.3.6 HcBufferStatus register (R/W: 0334h) . . . . . . 8.3.7 ATL Done Timeout register (R/W: 0338h) . . . 8.3.8 Memory register (R/W: 033Ch) . . . . . . . . . . . 8.3.9 Edge Interrupt Count register (R/W: 0340h) . 8.3.10 DMA Start Address register (W: 0344h) . . . . 8.3.11 Power Down Control register (R/W: 0354h) . . 8.4 Interrupt registers . . . . . . . . . . . . . . . . . . . . . . 8.4.1 HcInterrupt register (R/W: 0310h) . . . . . . . . . 8.4.2 HcInterruptEnable register (R/W: 0314h) . . . . 8.4.3 ISO IRQ MASK OR register (R/W: 0318h). . . 8.4.4 INT IRQ MASK OR register (R/W: 031Ch) . . 8.4.5 ATL IRQ MASK OR register (R/W: 0320h). . . 8.4.6 ISO IRQ MASK AND register (R/W: 0324h) . 8.4.7 INT IRQ MASK AND register (R/W: 0328h). . 8.4.8 ATL IRQ MASK AND register (R/W: 032Ch) . 8.5 Philips Transfer Descriptor . . . . . . . . . . . . . . . 8.5.1 High-speed bulk IN and OUT, QHA . . . . . . . . 8.5.2 High-speed isochronous IN and OUT, iTD . . . 8.5.3 High-speed interrupt IN and OUT, QHP . . . . . 8.5.4 Start and complete split for bulk, QHA-SS/CS 8.5.5 Start and complete split for isochronous, SiTD 8.5.6 Start and complete split for interrupt . . . . . . . 9 OTG Controller . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Dual-role device . . . . . . . . . . . . . . . . . . . . . . . 9.3 Session Request Protocol (SRP) . . . . . . . . . . 9.3.1 B-device initiating SRP. . . . . . . . . . . . . . . . . . 9.3.2 A-device responding to SRP . . . . . . . . . . . . . 9.4 Host Negotiation Protocol (HNP) . . . . . . . . . . 9.4.1 Sequence of HNP events . . . . . . . . . . . . . . . . 9.4.2 OTG state diagrams . . . . . . . . . . . . . . . . . . . . 9.4.3 HNP implementation and OTG state machine 9.5 OTG Controller registers . . . . . . . . . . . . . . . . 40 40 40 41 41 41 42 42 42 42 42 44 44 44 45 46 47 47 48 49 50 52 52 54 56 56 56 56 57 57 57 60 64 68 72 76 80 84 84 84 85 85 85 86 86 87 89 90
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9397 750 13258
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 12 January 2005
156 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
10.6.4 DMA Hardware register (R/W: 023Ch). . . . . 10.6.5 DMA Interrupt Reason register (R/W: 0250h) 10.6.6 DMA Interrupt Enable register (R/W: 0254h) 10.6.7 DMA Endpoint register (R/W: 0258h). . . . . . 10.6.8 DMA Burst Counter register (R/W: 0264h). . 10.7 General registers . . . . . . . . . . . . . . . . . . . . . 10.7.1 DcInterrupt register (R/W: 0218h) . . . . . . . . 10.7.2 DcChipID register (R: 0270h). . . . . . . . . . . . 10.7.3 Frame Number register (R: 0274h) . . . . . . . 10.7.4 DcScratch register (R/W: 0278h) . . . . . . . . . 10.7.5 Unlock Device register (W: 027Ch) . . . . . . . 10.7.6 Interrupt Pulse Width register (R/W: 0280h) 10.7.7 Test Mode register (R/W: 0284h) . . . . . . . . . 11 Power consumption . . . . . . . . . . . . . . . . . . . 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . 13 Recommended operating conditions . . . . . 14 Static characteristics . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . 15.1 Host timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1 PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1.1 Register or memory write . . . . . . . . . . . . . . . 15.1.1.2 Register read . . . . . . . . . . . . . . . . . . . . . . . . 15.1.1.3 Memory read . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2 DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . 15.1.2.1 Single cycle: DMA read . . . . . . . . . . . . . . . . 15.1.2.2 Single cycle: DMA write . . . . . . . . . . . . . . . . 15.1.2.3 Multicycle: DMA read . . . . . . . . . . . . . . . . . . 15.1.2.4 Multicycle: DMA write. . . . . . . . . . . . . . . . . . 15.2 Peripheral timing . . . . . . . . . . . . . . . . . . . . . 15.2.1 PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.1.1 PIO register read or write . . . . . . . . . . . . . . . 15.2.2 DMA timing. . . . . . . . . . . . . . . . . . . . . . . . . . 15.2.2.1 DMA read or write . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 Introduction to soldering surface mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . 17.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . 17.4 Manual soldering . . . . . . . . . . . . . . . . . . . . . 17.5 Package related soldering information . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 19 References . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status. . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 117 118 119 120 120 121 121 123 123 124 124 125 125 127 128 128 129 132 134 134 134 135 136 137 137 138 139 140 141 141 141 143 143 145 147 147 147 147 148 148 149 150 150 151 151 151 151
Device Identification registers . . . . . . . . . . . . . 91 Vendor ID register (R: 0370h). . . . . . . . . . . . . 91 Product ID register (R: 0372h) . . . . . . . . . . . . 91 OTG Control register . . . . . . . . . . . . . . . . . . . 92 OTG Control register (S/C: 0374h/0376h) . . . 92 OTG Interrupt registers. . . . . . . . . . . . . . . . . . 93 OTG Status register (R: 0378h) . . . . . . . . . . . 93 OTG Interrupt Latch register (S/C: 037Ch/037Eh) . . . . . . . . . . . . . . . . . . . . 94 9.5.3.3 OTG Interrupt Enable Fall register (S/C: 0380h/0382h) . . . . . . . . . . . . . . . . . . . . 95 9.5.3.4 OTG Interrupt Enable Rise register (S/C: 0384h/0386h) . . . . . . . . . . . . . . . . . . . . 95 9.5.4 OTG Timer register . . . . . . . . . . . . . . . . . . . . . 96 9.5.4.1 OTG Timer register (Low word S/C: 0388h/038Ah; high word S/C: 038Ch/038Eh) . . . . . . . . . . . . 96 10 Peripheral Controller . . . . . . . . . . . . . . . . . . . . 98 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 10.1.1 Direct Memory Access (DMA) . . . . . . . . . . . . 98 10.1.1.1 DMA for the IN endpoint . . . . . . . . . . . . . . . . . 98 10.1.1.2 DMA for the OUT endpoint . . . . . . . . . . . . . . . 98 10.1.1.3 DMA initialization . . . . . . . . . . . . . . . . . . . . . . 98 10.1.1.4 Starting DMA . . . . . . . . . . . . . . . . . . . . . . . . . 99 10.1.1.5 DMA stop and interrupt handling . . . . . . . . . . 99 10.2 Endpoint description . . . . . . . . . . . . . . . . . . . 100 10.3 Differences between the ISP1761 and ISP1582 Peripheral Controller . . . . . . . . . . . . . . . . . . . 101 10.3.1 ISP1761 initialization registers . . . . . . . . . . . 101 10.3.2 ISP1761 DMA . . . . . . . . . . . . . . . . . . . . . . . . 101 10.3.3 ISP1761 peripheral suspend indication . . . . 101 10.3.4 ISP1761 interrupt and DMA common mode . 101 10.4 Peripheral Controller-specific registers . . . . . 102 10.4.1 Address register (R/W: 0200h) . . . . . . . . . . . 102 10.4.2 Mode register (R/W: 020Ch). . . . . . . . . . . . . 103 10.4.3 Interrupt Configuration register (R/W: 0210h) 104 10.4.4 Debug register (R/W: 0212h) . . . . . . . . . . . . 105 10.4.5 DcInterruptEnable register (R/W: 0214h) . . . 106 10.5 Data flow registers . . . . . . . . . . . . . . . . . . . . 107 10.5.1 Endpoint Index register (R/W: 022Ch) . . . . . 107 10.5.2 Control Function register (R/W: 0228h) . . . . 109 10.5.3 Data Port register (R/W: 0220h) . . . . . . . . . . 109 10.5.4 Buffer Length register (R/W: 021Ch) . . . . . . 110 10.5.5 DcBufferStatus register (R/W: 021Eh) . . . . . 111 10.5.6 Endpoint MaxPacketSize register (R/W: 0204h) . . . . . . . . . . . . . . . . . . . . . . . . 111 10.5.7 Endpoint Type register (R/W: 0208h) . . . . . . 113 10.6 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . 113 10.6.1 DMA Command register (W: 0230h) . . . . . . 114 10.6.2 DMA Transfer Counter register (R/W: 0234h) 115 10.6.3 DcDMAConfiguration register (R/W: 0238h). 116
9.5.1 9.5.1.1 9.5.1.2 9.5.2 9.5.2.1 9.5.3 9.5.3.1 9.5.3.2
continued >>
9397 750 13258
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 01 -- 12 January 2005
157 of 158
Philips Semiconductors
ISP1761
Hi-Speed USB OTG controller
25
Contact information . . . . . . . . . . . . . . . . . . . 151
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 12 January 2005 Document number: 9397 750 13258
Published in The Netherlands

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